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rev. a a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 ad9891/ad9895 ccd signal processors with precision timing generator pxga is a registered trademark and precision timing is a trademark of analog devices, inc. features ad9891: 10-bit 20 mhz version ad9895: 12-bit 30 mhz version correlated double sampler (cds) 4 6 db pixel gain amplifier ( pxga ) 2 db to 36 db 10-bit variable gain amplifier (vga) 10-bit 20 mhz a/d converter (ad9891) 12-bit 30 mhz a/d converter (ad9895) black level clamp with variable level control complete on-chip timing generator precision timing core with 1 ns resolution on-chip 5 v horizontal and rg drivers 2-phase and 4-phase h-clock modes 4-phase vertical transfer clocks electronic and mechanical shutter modes on-chip driver for external crystal on-chip sync generator with external sync option 64-lead cspbga package applications digital still cameras digital video camcorders industrial imaging functional block diagram ad9891/ad9895 pxga cds clamp vga clamp adc 10 or 12 dclk clpob/pblk fd/ld mshut strobe clo cli dout vref 2db to 36db horizontal drivers v- h control 4 4 8 rg h1h4 v1v4 vsg1vsg8 vrt vrb precision timing generator sync generator internal clocks vsub subck hd vd sync internal registers sl sck data ccdin 4db 6db product description the ad9891 and ad9895 are highly integrated ccd signal processors for digital still camera applications. both include a complete analog front end with a/d conversion combined with a full-function programmable timing generator. a precision timing core allows adjustment of high speed clocks with 1 ns resolution at 20 mhz operation and 700 ps resolution at 30 mhz operation. the ad9891 is specified at pixel rates of up to 20 mhz, and the ad9895 is specified at 30 mhz. the analog front end includes black level clamping, cds, pxga , vga, and a 10-bit or 12-bit a/d converter. the timing generator provides all the necessary ccd clocks: rg, h-clocks, v-clocks, sensor gate pulses, substrate clock, and substrate bias control. operation is programmed using a 3-wire serial interface. packaged in a space-saving 64-lead cspbga, the ad9891 and ad9895 are specified over an operating temperature range of C 20 c to +85 c.
rev. a e2e ad9891/ad9895 table of contents specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 digital specifications . . . . . . . . . . . . . . . . . . . . . 3 ad9891 analog specifications . . . . . . . . . . . . . . 4 ad9895 analog specifications . . . . . . . . . . . . . . 5 timing specifications . . . . . . . . . . . . . . . . . . . . . . 6 package thermal characteristics . . . . . . . . 6 absolute maximum ratings . . . . . . . . . . . . . . . . . 6 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configuration-ad9891 . . . . . . . . . . . . . . . . . . . 7 pin function descriptions-ad9891 . . . . . . . . . . . 7 pin configuration-ad9895 . . . . . . . . . . . . . . . . . . . 8 pin function descriptions-ad9895 . . . . . . . . . . . 8 specification definitions . . . . . . . . . . . . . . . . . . . 9 equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance characteristics . . . . 10 system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 typical system block diagram . . . . . . . . . . . . . . . . . . . . 11 precision timing high speed timing generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 timing resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 high speed clock programmability . . . . . . . . . . . . . . . . . .12 h-driver and rg outputs . . . . . . . . . . . . . . . . . . . . . . . . .13 digital data outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 horizontal clamping and blanking . . . . . . . . 15 individual clpob, clpdm, and pblk sequences . . . . . 15 individual hblk sequences . . . . . . . . . . . . . . . . . . . . . . .15 horizontal sequence control . . . . . . . . . . . . . . . . . . . . . . .15 vertical timing generation . . . . . . . . . . . . . . . .17 individual vertical sequences . . . . . . . . . . . . . . . . . . . . . .18 individual vertical regions . . . . . . . . . . . . . . . . . . . . . . . .19 complete field: combining the regions . . . . . . . . . . . . . . 20 vertical sequence alteration . . . . . . . . . . . . . . . . . . . . . . .21 second vertical sequence during vsg lines . . . . . . . . . . 22 vertical sweep mode operation . . . . . . . . . . . . . . . . . . . .22 vertical multiplier mode . . . . . . . . . . . . . . . . . . . . . . . . . .24 frame transfer ccd mode . . . . . . . . . . . . . . . . . . . . . . 24 vertical sensor gate (shift gate) timing . . . . . . . . . . . . .25 shutter timing control . . . . . . . . . . . . . . . . . . . .26 normal shutter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 high precision shutter mode . . . . . . . . . . . . . . . . . . . . . . .26 low speed shutter mode . . . . . . . . . . . . . . . . . . . . . . . . .26 subck suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 readout after exposure . . . . . . . . . . . . . . . . . . . . . . . . . . .27 vsub control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 mshut and strobe control . . . . . . . . . . . . . . . . . . . .27 example of exposure and readout of interlaced frame . . . 29 analog front end description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 dc restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 correlated double sampler . . . . . . . . . . . . . . . . . . . . . . . 30 input clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 pxga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 pxga color steering mode timing . . . . . . . . . . . . . . . . 31 variable gain amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 33 pxga and vga gain curves . . . . . . . . . . . . . . . . . . . . . 33 optical black clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 power-up and synchronization . . . . . . . . . . . . 34 recommended power-up sequence for master mode . . . . 34 sync during master mode operation . . . . . . . . . . . . . . .35 synchronization in slave mode . . . . . . . . . . . . . . . . . . . . .35 power-down mode operation . . . . . . . . . . . . . . 35 horizontal timing sequence example . . . . . 37 vertical timing example . . . . . . . . . . . . . . . . . . . 39 circuit layout information . . . . . . . . . . . . . . . .40 serial interface timing . . . . . . . . . . . . . . . . . . . . .41 notes about accessing a double-wide register . . . . . . . 41 notes on register listing . . . . . . . . . . . . . . . . . . 42 complete register listing . . . . . . . . . . . . . . . . . 43 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 57 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
rev. a e3e ad9891/ad9895especifications parameter min typ max unit temperature range operating ? 20 +85 c storage ? 65 +150 c power supply voltage avdd1, avdd2 (afe analog supply) 2.7 3.0 3.6 v tcvdd (timing core analog supply) 2.7 3.0 3.6 v rgvdd (rg driver) 3.0 5.0 5.25 v hvdd (h1 ? h4 drivers) 3.0 5.0 5.25 v drvdd (data output drivers) 2.7 3.0 3.6 v dvdd (digital) 2.7 3.0 3.6 v power dissipation ? ad9891 (see tpc 1 for power curves) 20 mhz, typ supply levels, 100 pf h1 ? h4 loading 380 mw power from hvdd only * 220 mw power-down 1 mode 42 mw power-down 2 mode 8 mw power-down 3 mode 2.5 mw power dissipation ? ad9895 (see tpc 4 for power curves) 30 mhz, typ supply levels, 100 pf h1 ? h4 loading 600 mw power from hvdd only * 320 mw power-down 1 mode 138 mw power-down 2 mode 22 mw power-down 3 mode 2.5 mw maximum clock rate (cli) ad9891 20 mhz ad9895 30 mhz * the total power dissipated by the hvdd supply may be approximated using the equation: total hvdd power = [ c load
rev. a e4e ad9891/ad9895 ad9891eanalog specifications parameter min typ max unit notes cds gain 0 db allowable ccd reset transient 500 mv input signal characteristics * max input range before saturation 1.0 v p-p max ccd black pixel amplitude 200 mv pixel gain amplifier ( pxga ) max input range 1.0 v p-p max output range 1.6 v p-p gain control resolution 64 steps gain monotonicity guaranteed gain range min gain ( pxga code 32) ? 2.5 db med gain ( pxga code 0) +3.5 db default setting max gain ( pxga code 31) +9.5 db variable gain amplifier (vga) max input range 1.6 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity guaranteed gain range low gain (vga code 70) 2 db max gain (vga code 1023) 36 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level 0 lsb max clamp level 63.75 lsb a/d converter resolution 10 bits differential nonlinearity (dnl) 0.4 1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (vrt) 2.0 v reference bottom voltage (vrb) 1.0 v system performance includes entire signal chain gain accuracy includes 4 db default pxga gain low gain (vga code 70) 5 6 7 db gain = (0.035
rev. a ad9891/ad9895 e5e ad9895eanalog specifications parameter min typ max unit notes cds gain 0 db allowable ccd reset transient 500 mv input signal characteristics * max input range before saturation 1.0 v p-p max ccd black pixel amplitude 200 mv pixel gain amplifier ( pxga ) max input range 1.0 v p-p max output range 1.6 v p-p gain control resolution 64 steps gain monotonicity guaranteed gain range min gain ( pxga code 32) ? 2.5 db med gain ( pxga code 0) +3.5 db default setting max gain ( pxga code 31) +9.5 db variable gain amplifier (vga) max input range 1.6 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity guaranteed gain range low gain (vga code 70) 2 db max gain (vga code 1023) 36 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level 0 lsb max clamp level 255 lsb a/d converter resolution 12 bits differential nonlinearity (dnl) 0.5 1.0 lsb no missing codes guaranteed full-scale input voltage 2.0 v voltage reference reference top voltage (vrt) 2.0 v reference bottom voltage (vrb) 1.0 v system performance includes entire signal chain gain accuracy includes 4 db default pxga gain low gain (vga code 70) 5 6 7 db gain = (0.035
rev. a e6e ad9891/ad9895 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9891 and ad9895 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings with respect parameter to min max unit avdd1, avdd2 avss ? 0.3 +3.9 v tcvdd tcvss ? 0.3 +3.9 v hvdd hvss ? 0.3 +5.5 v rgvdd rgvss ? 0.3 +5.5 v dvdd dvss ? 0.3 +3.9 v drvdd drvss ? 0.3 +3.9 v rg output rgvss ? 0.3 rgvdd + 0.3 v h1 ? h4 output hvss ? 0.3 hvdd + 0.3 v digital outputs dvss ? 0.3 dvdd + 0.3 v digital inputs dvss ? 0.3 dvdd + 0.3 v sck, sl, sdata dvss ? 0.3 dvdd + 0.3 v vrt, vrb avss ? 0.3 avdd + 0.3 v byp1 ? byp3, ccdin avss ? 0.3 avdd + 0.3 v junction temperature 150 c lead temperature, 10 sec 350 c ordering guide temperature package package model range description option ad9891kbc ? 20 c to +85 c cspbga bc-64 ad9895kbc ? 20 c to +85 c cspbga bc-64 package thermal characteristics thermal resistance
rev. a ad9891/ad9895 e7e ad9891 pin configuration a b c d e f g h j k ad9891 top view (not to scale) 1234567 910 8 a1 corner index area pin function descriptions 1 pin mnemonic type 2 description k9 vsg5 do ccd sensor gate pulse 5 j9 vsg 6d o ccd sensor gate pulse 6 k10 vsg 7d o ccd sensor gate pulse 7 j10 vsg8 do ccd sensor gate pulse 8 h10 h1 do ccd horizontal clock 1 h9 h2 do ccd horizontal clock 2 g10 hvdd p h1 ? h4 driver supply g9 hvss p h1 ? h4 driver ground f10 h3 do ccd horizontal clock 3 f9 h4 do ccd horizontal clock 4 e10 rgvdd p rg driver supply e9 rgvss p rg d river ground d9 rg do ccd reset gate clock d10 clo do reference clock output for crystal c10 cli di reference clock input b10 tcvdd p analog supply for timing core c9 tcvss p analog ground for timing core a10 avdd1 p analog supply for afe b9 avss1 p analog g round for afe a9 byp1 ao analog circuit bypass b8 byp2 ao analog circuit bypass a8 ccdin ai ccd signal input a7 byp3 ao analog circuit bypass b7 avdd2 p analog supply for afe b6 avss2 p analog g round for afe a6 refb ao voltage reference bottom bypass a5 reft ao v oltage reference top bypass b5 sl di 3-wire serial load pulse a4 sdi di 3-wire serial data input b4 sck di 3-wire serial clock a3 mshut do mech anical shutter pulse b3 strobe do strobe pulse b2 dvss p digital ground a2 dvdd p digital supply for vsg, v1 ? v4, hd, vd, mshut, strobe, and serial interface notes 1 see figure 50 for circuit configuration. 2 ai = analog input, ao = analog output, di = digital input, do = digital output, dio = digital input/output, p = power. 3 in register readback mode 4 in frame transfer ccd mode pin mnemonic type 2 description a1 vd do vertical sync pulse (input for slave mode, output for master mode) b1 hd do horizontal sync pulse (input for slave mode, output for master mode) c1 syn cd ie xternal system sync input c2 ld/ fd do line or field designator output d1 dclk do data clock output d2 clpob/ do clpob or pblk output pblk e1 nc not internally connected e2 nc not internally connected f2 do/sdo do data o utput (lsb) (also serial data output 3 ) f1 d1 do data output g2 d2 do data output g1 d3 do data output h2 d4 do data output h1 d5 do data output j2 d6 do data output j1 d7 do data output k2 d8 do data output k1 d9 do data output (msb) k3 drvdd p data output driver supply k4 drvss p data output driver ground j3 vsub do ccd substrate bias j4 subck do ccd substrate clock (e-shutter) k5 v1 do ccd vertical transfer clock 1 j5 v2 do ccd vertical transfer clock 2 k6 v3 do ccd vertical transfer clock 3 j6 v4 do ccd vertical transfer clock 4 k7 vs g 1/v 5d o ccd sensor gate pulse 1 (also v5 4 ) j7 vs g 2/v 6d o ccd sensor gate pulse 2 (also v6 4 ) k8 vs g 3/v 7d o ccd sensor gate pulse 3 (also v7 4 ) j8 vs g 4/v 8d o ccd sensor gate pulse 4 (also v8 4 )
rev. a e8e ad9891/ad9895 ad9895 pin configuration a b c d e f g h j k ad9895 top view (not to scale) 1234567 910 8 a1 corner index area pin function descriptions 1 pin mnemonic type 2 description k9 vsg5 do ccd sensor gate pulse 5 j9 vsg 6d o ccd sensor gate pulse 6 k10 vsg 7d o ccd sensor gate pulse 7 j10 vsg8 do ccd sensor gate pulse 8 h10 h1 do ccd horizontal clock 1 h9 h2 do ccd horizontal clock 2 g10 hvdd p h1 ? h4 driver supply g9 hvss p h1 ? h4 driver ground f10 h3 do ccd horizontal clock 3 f9 h4 do ccd horizontal clock 4 e10 rgvdd p rg driver supply e9 rgvss p rg d river ground d9 rg do ccd reset gate clock d10 clo do reference clock output for crystal c10 cli di reference clock input b10 tcvdd p analog supply for timing core c9 tcvss p analog ground for timing core a10 avdd1 p analog supply for afe b9 avss1 p analog g round for afe a9 byp1 ao analog circuit bypass b8 byp2 ao analog circuit bypass a8 ccdin ai ccd signal input a7 byp3 ao analog circuit bypass b7 avdd2 p analog supply for afe b6 avss2 p analog g round for afe a6 refb ao v oltage reference bottom bypass a5 reft ao v oltage reference top bypass b5 sl di 3-wire serial load pulse a4 sdi di 3-wire serial data input b4 sck di 3-wire serial clock a3 mshut do m echanical shutter pulse b3 strobe do strobe pulse b2 dvss p digital ground a2 dvdd p digital supply for vsg, v1 ? v4, hd, vd, mshut, strobe, and serial interface notes 1 see figure 50 for circuit configuration. 2 ai = analog input, ao = analog output, di = digital input, do = digital output, dio = digital input/output, p = power. 3 in register readback mode 4 in frame transfer ccd mode pin mnemonic type 2 description a1 vd do vertical sync pulse (input for slave mode, output for master mode) b1 hd do horizontal sync pulse (input for slave mode, output for master mode) c1 syn cd ie xternal system sync input c2 ld/ fd do line or field designator output d1 dclk do data clock output d2 clpob/ do clpob or pblk output pblk e2 do do data output (lsb) e1 d1 do data output f2 d2/sdo do data output (also serial data output 3 ) f1 d3 do data output g2 d4 do data output g1 d5 do data output h2 d6 do data output h1 d7 do data output j2 d8 do data output j1 d9 do data output k2 d10 do data output k1 d11 do data output (msb) k3 drvdd p data output driver supply k4 drvss p data output driver ground j3 vsub do ccd substrate bias j4 subck do ccd substrate clock (e-shutter) k5 v1 do ccd vertical transfer clock 1 j5 v2 do ccd vertical transfer clock 2 k6 v3 do ccd vertical transfer clock 3 j6 v4 do ccd vertical transfer clock 4 k7 vsg 1/v 5d o ccd sensor gate pulse 1 (also v5 4 ) j7 vsg 2/v 6d o ccd sensor gate pulse 2 (also v6 4 ) k8 vsg 3/v 7d o ccd sensor gate pulse 3 (also v7 4 ) j8 vsg 4/v 8d o ccd sensor gate pulse 4 (also v8 4 )
rev. a ad9891/ad9895 e9e specification definitions differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus, every code must have a finite width. no missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ad9891/ad9895 from a true straight line. the point used as ? zero scale ? occurs 0.5 lsb before the first code transition. ? positive full scale ? is defined as a level 1 and 0.5 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a equivalent circuits percentage of the 2 v adc full-scale signal. the input signal is always appropriately gained up to fill the adc ? s full-scale range. total output noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the specified gain setting. the output noise can be converted to an equivalent voltage, using the relationship 1 lsb = ( adc full scale /2 n codes ) when n is the bit resolution of the adc. for the ad9891, 1 lsb is 2 mv, wh ile for the ad9895, 1 lsb is 0.5 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. the psr specification is calculated from the change in the data outputs for a given step change in the supply voltage. hvdd or rgvdd hvss or rgvss output rg, h1eh4 enable figure 4. h1eh4, rg drivers r av dd1 a vss1 avss1 figure 1. ccdin dvdd d vss drvss drvdd three- state data dout figure 2. digital data outputs dvdd d vss 330 figure 3. digital inputs
rev. a e10e ad9891/ad9895etypical performance characteristics sample rate e mhz 440 320 200 20 10 power dissipation e mw 240 280 360 400 15 v dd = 3.3v v dd = 3.0v v dd = 2.7v rgvdd = hvdd = 5.0v tpc 1. ad9891 power vs. sample rate 0 1000 400 200 600 800 0 e1.0 1.0 0.5 e0.5 tpc 2. ad9891 typical dnl performance vga gain code e lsb 4 2 0 0 1000 400 output noise e lsb 200 1 600 3 800 tpc 3. ad9891 output noise vs. vga gain sample rate e mhz 725 500 275 30 10 power dissipation e mw 350 425 575 650 20 v dd = 3.3v v dd = 3.0v v dd = 2.7v rgvdd = hvdd = 5.0v tpc 4. ad9895 power vs. sample rate 0 4000 1600 800 2400 3200 0 e1.0 1.0 0.5 e0.5 tpc 5. ad9895 typical dnl performance vga gain code e lsb 24 12 0 0 1000 400 output noise e lsb 200 6 600 18 800 15 3 9 21 tpc 6. ad9895 output noise vs. vga gain
rev. a ad9891/ad9895 e11e system overview figure 5 shows the typical system block diagram for the ad9891/ ad9895 used in master mode. the ccd output is processed by the ad9891/ad9895 ? s afe circuitry, which consists of a cds, pxga , vga, black level clamp, and an a/d converter. the digi- tized pixel information is sent to the digital image processor chip, which performs the post-processing and compression. to operate the ccd, all ccd timing parameters are programmed into the ad9891/ad9895 from the system microprocessor, through the 3-wire serial interface. from the system master clock, cli, pro- vided by the image processor or external crystal, the ad9891/ ad9895 generates all of the ccd ? s horizontal and vertical clocks and all internal afe clocks. exter nal synchronization is provided by a sync pulse from the microprocessor, which will reset internal counters and resync the vd and hd outputs. ccdin mshut strobe h1eh4, rg, vsub v1ev4, vsg1evsg8, subck ccd v- driver ad989x digital image processing asic p dout dclk clpob/pblk ld/fd hd, vd cli serial interface sync figure 5. typical system block diagram, master mode alternatively, the ad9891/ad9895 may be operated in slave mode, in which the vd and hd are provided externally from the image processor. in this mode, all ad9891/ad9895 timing will be synchronized with vd and hd. the h-drivers for h1 ? h4 and rg are included in the ad9891/ ad9895, allowing these clocks to be directly connected to the ccd. h-drive voltage of up to 5 v is supported. an external v-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock. the ad9891/ad9895 also includes programmable mshut and s trobe outputs, which may be used to trigger mechani- cal shutter and strobe (flash) circuitry. figure 6 shows the horizontal and vertical counter dimensions for the ad9891/ad9895. all internal horizontal and vertical clocking is programmed using these dimensions to specify line and pixel locations. 12-bit horizontal = 4096 pixels max 12-bit vertical = 4096 lines max maximum field dimensions figure 6. vertical and horizontal counters
rev. a e12e ad9891/ad9895 precision timing high speed timing generation the ad9891/ad9895 generates flexible, high speed timing signals using the precision timing core. this core is the founda- tion for generating the timing used for both the ccd and the afe: the reset gate rg, horizontal drivers h1 ? h4, and the shp/shd sample clocks. a unique architecture makes it rou- tine for the system designer to optimize image quality by providing precise control over the horizontal ccd readout and the afe correlated double sampling. the high speed timing of the ad9891/ad9895 operates the same in either master or slave mode configuration. timing resolution the precision timing core uses a 1
rev. a ad9891/ad9895 e13e the corresponding edge locations. figure 10 shows the range and default locations of the high speed clock signals. h-driver and rg outputs in addition to the programmable timing positions, the ad9891/ ad9895 features on-chip output drivers for the rg and h1 ? h4 outputs. these drivers are powerful enough to directly drive the ccd inputs. the h-driver current can be adjusted for optimum rise/fall time into a particular load by using the drv registers (addr x0e1 to x0e4). the rg drive current is adjustable using the rgdrv register (addr x0e8). each 3-bit drv register is adjust able in 3.5 ma increments, with the minimum setting of 0 equal to off or three-state, and the maximum setting of 7 equal to 24.5 ma. as shown in figure 11, the h2 and h4 outputs are inverses of h1 and h3, respectively. the internal propagation delay resulting from the signal inversion is less than 1 ns, which is significantly less than the typical rise time driving the ccd load. this results in an h1/h2 crossover voltage at approximately 50% of the out- put swing. the crossover voltage is not programmable. digital data outputs the ad9891/ad9895 data output and dclk phase are pro- grammable using the doutphase register (addr x01d). any edge from 0 to 47 may be programmed, as shown in figure 12. normally, the dout and dclk signals will track in phase, based on the doutphase register contents. the dclk output phase can also be held fixed with respect to the data outputs, by changing the dclkmode register (addr x01e) high. in this mode, the dclk output will remain at a fixed phase equal to clo (the inverse of cli) while the data output phase is still programmable. there is a fixed output delay from the dclk rising edge to the dout transition, called t od . this delay can be programmed to four values between 0 ns and 12 ns, using the dout_delay register (addr x032). the default value is 8 ns. table i. h1eh4, rg, shp, and shd timing parameters register length range description pol 1b high/low polarity control for h1, h3, and rg (0 = no inversion, 1 = inversion) posloc 6b 0 ? 47 edge location positive edge location for h1, h3, and rg sample location for shp, shd negloc 6b 0 ? 47 edge location negative edge location for h1, h3, and rg drv 3b 0 ? 7 current steps drive current for h1 ? h4 and rg outputs (3.5 ma per step) h1/h3 h2/h4 rg using the same toggle positions for h1 and h3 generates standard 2-phase h-clocking. ccd signal figure 9. 2-phase h-clock operation table ii. precision timing edge locations quadrant edge location (dec) register value (dec) register value (bin) i0 to 11 0 to 11 000000 to 001011 ii 12 to 23 16 to 27 010000 to 011011 iii 24 to 35 32 to 43 100000 to 101011 iv 36 to 47 48 to 59 110000 to 111011
rev. a e14e ad9891/ad9895 p[0] pixel period rg h1/h3 rgf[12] p[48] = p[0] hf[24] shp[28] ccd signal p[24] p[12] p[36] hr[0] rgr[0] shd[48] notes all signal edges are fully programmable to any of the 48 positions within one pixel period. default positions for each signal are shown. position t s1 figure 10. high speed clock default and programmable locations fixed crossover voltage h1/h3 h2/h4 t pd h2/h4 h1/h3 t rise t pd < t rise figure 11. h-clock inverse phase relationship notes data output (dout) and dclk phase are adjustable with respect to the pixel period. within 1 clock period, the data transition can be programmed to 48 different locations. output delay ( t od ) from dclk rising edge to dout rising edge is programmable. p[0] p[48] = p[0] pixel period p[12] p[24] p[36] dout dclk t od figure 12. digital output phase adjustment
rev. a ad9891/ad9895 e15e horizontal clamping and blanking t he ad 989 1/ad9895 ? s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. as with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple regions during image readout. this allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts. individual clpob, clpdm, and pblk sequences the afe horizontal timing consists of clpob, clpdm, and pblk, as shown in figure 13. these three signals are indepen- dently programmed using the registers in table iii. spol is the start polarity for the signal, and tog1 and tog2 are the first and second toggle positions of the pulse. all three signals are active low and should be programmed accordingly. up to four individual sequences can be created for each signal. to simplify the programming requirements, the clpdm signal will track the clpob signal by default. if separate control of the clpdm signal is desired, the single_clamp register (addr x031) should be set low. individual hblk sequences the hblk programmable timing shown in figure 14 is similar to clpob, clpdm, and pblk. however, there is no start polarity control. only the toggle positions are used to designate the start and the stop positions of the blanking period. addition- ally, there is a polarity control , hblkmask, that designates the polarity of the horizontal clock signals h1 ? h4 during the blank- ing period. setting hblkmask high will set h1 = h3 = low and h2 = h4 = high during the blanking, as shown in figure 15. up to four individual sequences are available for hblk. horizontal sequence control the ad9891/ad9895 use sequence change positions ( scp) and s equence pointers (sptr) to organize the individual hori- hd clpob clpdm pblk programmable settings: 1: start polarity (clamp and blank region are active low) 2: 1st toggle position 3: 2nd toggle position clamp clamp 123 figure 13. clamp and preblank pulse placement hd hblk programmable settings: 1: 1st toggle position = start of blanking 2: 2nd toggle position = end of blanking blank blank 12 figure 14. horizontal blanking (hblk) pulse placement hd hblk the polarity of h1 during blanking is programmable (h2 is opposite polarity of h1) h1/h3 h1/h3 h2/h4 figure 15. hblk masking control
rev. a e16e ad9891/ad9895 table iii. clpob, clpdm, and pblk individual sequence parameters register length range description spol 1b high/low starting polarity of vertical transfer pulse for sequences 0 ? 3 tog1 12b 0 ? 4095 pixel location first toggle position within line for sequences 0 ? 3 tog2 12b 0 ? 4095 pixel location second toggle position within line for sequences 0 ? 3 table iv. hblk individual sequence parameters register length range description hblkmask 1b high/low masking polarity for h1 for sequences 0 ? 3 (0 = h1 low, 1 = h1 high) hblktog1 12b 0 ? 4095 pixel location first toggle position within line for sequences 0 ? 3 hblktog2 12b 0 ? 4095 pixel location second toggle position within line for sequences 0 ? 3 table v. horizontal sequence control parameters for clpob, clpdm, and pblk register length range description scp1 ? scp3 12b 0 ? 4095 line number clpob/pblk scp to define horizontal regions 0 ? 3 sptr0 ? sptr3 2b 0 ? 3 sequence number sequence pointer for horizontal regions 0 ? 3 table vi. horizontal sequence control parameters for hblk register length range description vtprcp1 ? 12b 0 ? 4095 line number vertical region change positions (see table ix.) vtprcp7 hblksptr0 ? 2b 0 ? 3 sequence number sequence pointer for hblk regions 0 ? 7 hblksptr7 up to four individual horizontal clamp and blanking regions may be programmed with- in a single field, using the sequence change positions. se quence change position #1 se quence change position #2 se quence change position #3 single field (1 vd interval) clamp and pblk sequence region 1 se quence change position #0 (v-counter = 0) clamp and pblk sequence region 4 clamp and pblk sequence region 3 clamp and pblk sequence region 2 figure 16. clamp and blanking sequence flexibility zontal sequences. up to four scps are available to divide the readout into four separate regions, as shown in figure 16. the scp0 is always hard-coded to line 0, and scp1 ? scp3 are register programmable. during each region bound by the scp, the sptr registers designate which sequence is used by each signal. clpob and clpdm share the same scp, pblk has a separate set of scp, and hblk shares the vertical rcp (see vertical timing generation section ). for example, clpscp1 will define region 0 for clpob and clpdm, a nd in that region any of the four individual clpob and clpdm sequences may be selected with the sptr registers. the next scp defines a new r egion, and in that region each signal can be assigned to a different individual sequence. be- cause hblk shares the vertical rcp, there are up to eight reg i ons wh ere hblk sequences may be changed using the eight hblksptr registers.
rev. a ad9891/ad9895 e17e vertical timing generation the ad9891/ad9895 provide a very flexible solution for gener- ating vertical ccd timing and can support multiple ccds and different system architectures. the 4-phase vertical transfer clocks v1 ? v4 are used to shift each line of pixels into the hori- zontal output register of the ccd. the ad9891/ad9895 allow these outputs to be individually programmed into different pulse patterns. vertical sequence control registers then organize the individual vertical pulses into the desired ccd vertical timing arrangement. figure 17 shows an overview of how the vertical timing is gener- ated in three basic steps. first, the individual pulse patterns or sequences are created by using the vertical transfer pulse (vtp) registers. these sequences are a essentially a ? pool ? of pulse patterns that may be assigned to any of the v1-v4 outputs. sec- ond, individual regions are built by assigning a sequence to each of the v1 ? v4 outputs. up to five unique regions may be speci- fied. finally, the readout of the entire field is constructed by combining one or more of the individual regions sequentially. with up to eight region areas available, different steps of the readout such as high speed line shifts and vertical image transfer can be supported. us e region 2 for lines 1 to 20 us e region 1 for line 21 us e region 0 for lines 22 to 2000 us e region 2 for lines 2001 to 2020 * sequences may be shifted and/or inverted sequence 2 sequence 3 sequence 0 sequence 1 sequence 9 sequence 10 sequence 5 sequence 7 sequence 6 sequence 8 sequence 4 sequence 11 create the individual vertical sequences (maximum of 12 sequences). build the individual vertical regions by assigning each sequence to v1ev4 outputs (maximum of 5 regions). region 0 v1 (seq 0) v2 (seq 0 * ) v3 (seq 1) v4 (seq 1 * ) region 1 v1 (seq 2) v2 (seq 3) v3 (seq 4) v4 (seq 5) region 4 v1 (seq 6) v2 (seq 6 * ) v3 (seq 7) v4 (seq 7 * ) build the entire field readout by combining multiple regions (maximum of 8 combinations). figure 17. summary of vertical timing generation
rev. a e18e ad9891/ad9895 individual vertical sequences to generate the individual vertical sequences or patterns shown in figure 18, five registers are required for each sequence. table vii summarizes these registers and their respective bit lengths. the start polarity (vtppol) determines the starting polarity of the vertical sequence and can be programmed high or low. the first toggle position (vtptog1) and second toggle position (vtptog2) are the pixel locations within the line where the pulse transitions. a third toggle position (vtptog3) is also available for sequences 0 through 7. all toggle positions are 10-bit values, which limits the placement of a pulse to within 1024 pixels of a line. a separate register, vstart, sets the start position of the sequence within the line (see individual vertical regions section). the length (vtplen) register determines the num ber of pixels between each of the pulse repetitions, if any repetitions have been programmed. the number of repetitions (vtprep) simply determines the number of pulse repeti tions desired within a single line. programming ? 1 ? for vtprep gives a single pulse, while setting to ? 0 ? will provide a fixed dc output based on the start polarity value. there is a total of 12 individual sequences that may be programmed. when specifying the individual regions, each sequence may be assigned to any of the v1 ? v4 outputs. for example, figure 19 shows a typical 4-phase v-clock arrangement. two different sequences are needed to generate the different pulsewidths. the use of individual start positions for v1 ? v4 allows the four outputs to be generated from two sequences. figure 20 shows a slightly different v-clock arrangement in which v2, v3, and v4 are simply shifted and/or inverted versions of v1. only one individual sequence is needed because all signals have the same pulsewidth. the invert sequence registers (vinv) are used for v3 and v4 (see table vii). note that for added flexibility, the vtppol registers (start polarity) may be used as an extra toggle position. table vii. individual vtp sequence parameters register length range description vtppol 1b high/low starting polarity of vertical transfer pulse for each sequence 0 ? 11 vtptog1 10b 0 ? 1023 pixel location first toggle position within line for each sequence 0 ? 11 vtptog2 10b 0 ? 1023 pixel location second toggle position within line for each sequence 0 ? 11 vtptog3 10b 0 ? 1023 pixel location third toggle position within line for each sequence 0 ? 7 vtplen 10b 0 ? 1023 pixels length between pulse repetitions for each sequence 0 ? 11 vtprep 12b 0 ? 4095 pulses number of pulse repetitions for each sequence 0 ? 11 (0 = dc output) hd v1ev4 programmable settings for each sequence: 1: start polarity 2: 1st toggle position 3: 2nd toggle position (there is also a 3rd toggle position available for sequences 0 to 7) 4: length between repeats 5: number of repeats start position of sequence is individually programmable for each v1ev4 output 4 5 1 2 3 figure 18. individual vertical sequence programmability v1 v2 v1 uses sequence 0 v3 v4 hd v2 uses sequence 0, with different start position v3 uses sequence 1 v4 uses sequence 1, with different start position figure 19. example of separate v1ev4 signals using two individual sequences
rev. a ad9891/ad9895 e19e individual vertical regions the ad9891/ad9895 arranges the individual sequences into re- gions through the use of sequence pointers (sptr). within each region, different sequences may be assigned to each v-clock output. figure 21 shows the programmability of each region and table viii summ arizes the registers needed for generating each region. for each individual region, the line length (in pixels) is programmable using the hdlen registers. each region can have a different line length to accommodate various image readout techniques. the maximum number of pixels per line is 4096. also unique to each region are the sequence start positions for each v-output, which are programmed using the vstart registers. each vstart is a 12-bit value, allowing the start position to be placed anywhere in the line. there are five hdlen registers, one for each region. there is a total of 20 vstart registers: one for each v1 ? v4 output, for five different regions. note that the last line of the field is separately programmable using the hdlastlen register. the sequence pointer registers vxsptrfirst and vxsptrsecond assign the individual vertical sequences to each of the v-clock outputs (v1 ? v4) within a given region. typically, only the sptrfirst registers are used, with the sptrsecond registers reserved for generating line-by-line alternation (see vertical sequence alternation). any of the 12 individual sequences may also be inverted using the vxinvfirst and vxinvsecond registers, effectively dou- bling the number of sequences available. there is one sptrfirst register for each v-output, for a total of four regis- ters per region. if all five regions are used, there is a total of 20 sptrfirst registers. there is also the same number of sptrsecond registers, if alternation is required. note that the sptr registers are four bits wide; if a value greater than 11 is programmed, the vx output will be dc at the level of the vxinv register. v1 v2 v1 uses sequence 2 v3 v4 hd v2 uses sequence 2, with different start position v3 uses sequence 2, inverted v4 uses sequence 2, inverted, with different start position figure 20. example of inverted v1ev4 signals using one individual sequence with inversion hd v1ev4 programmable settings for each region: 1: start position of selected sequence is separately programmable for each output 2: hd line length 3: sequence pointers (sptr) to select an individual sequence for each output 4: any sequences may also be alternated for additional flexibility se quences a, b, c, d 1 2 3 figure 21. individual vertical region programmability
rev. a e20e ad9891/ad9895 complete field: combining the regions the individual regions are combined into a complete field readout by using region change positions (rcp) and region pointers (regptr). figure 22 shows how each field is divided into multiple regions. this allows the user to change the vertical timing during various stages of the image readout. the bound aries of each region are defined by the sequence change positions (rcp). each rcp is a 12-bit value representing the line number bounding the region. a total of seven rcps allow up to eight different region areas in the field to be defined. the first rcp is always hard-coded to zero, and the remaining seven are register programmable. note that there are only five possible individual regions that can be defined, but the eight region areas allow the same region to be used in more than one place during the field. within each region area, the region pointers specify which of the five individual regions will be used. there are eight region pointers, one for each region area. table ix summarizes the registers for the region change positions and region pointers. up to eight v-clock region areas may be defined within one field by using the region change position and the region pointers. region change postion #1 region change postion #2 region change postion #3 region change postion #4 region change postion #5 single field ( 1 vd interval) us e the region specified by region pointer 0 region change postion #0 (v-counter = 0) region change postion #6 region change postion #7 us e the region specified by region pointer 6 us e the region specified by region pointer 5 us e the region specified by region pointer 4 us e the region specified by region pointer 3 us e the region specified by region pointer 2 us e the region specified by region pointer 1 us e the region specified by region pointer 7 figure 22. complete field using multiple region areas table viii. individual vertical region parameters register length range description hdlen 12b 0 ? 4095 pixels hd line length for lines in each region 0 ? 4 vxstart 12b 0 ? 4095 pixel location sequence start position for each vx output in each region 0 ? 4 vxsptrfirst 4b sequence 0 ? 11 sequence pointer for vx output during each region 0 ? 4 (can be used with sptrsecond for alternation, see text) vxinvfirst 1b high/low when high, the polarity of sequence vxsptrfirst is inverted x is the v-output from 1 ? 4. table ix. complete vertical field registers register length range description vtprcp 12b 0 ? 4095 line location region change position for each region area in field vtpregptr 3b region 0 ? 4r egion pointer for each region area of field
rev. a ad9891/ad9895 e21e table x. vertical sequence alternation parameters register length range description vtpalt 1b enabled/disabled enables the line-by-line alternation (1 = enabled) vxsptrfirst 4b sequence 0 ? 11 sptr for vx output during each region 0 ? 4 for first lines vxinvfirst 1b high/low when high, the polarity of vxsptrfirst is inverted vxsptrsecond 4b sequence 0 ? 11 sptr for vx output during each region 0 ? 4 for second lines vxinvsecond 1b high/low when high, the polarity of vxsptrsecond is inverted x is the v-output from 1 ? 4. vertical sequence alternation the ad9891/ad9895 also supports line-by-line alternation of vertical sequences within any region, as shown in figure 23. table x summarizes the additional registers used to support differ- ent alter nation patterns. to create an alternating vertical pattern, the vxsptrfirst and vxsptrsecond registers are pro- grammed with the desired sequences to be alternated. the vtpalt register must be set high for that region to use alternation. if vtpalt is low, then the vxsptrsecond registers will be ignored. figure 24 shows an example of line- by-line alternation. region change postion #2 single field (1 vd interval) se cond lines f irst lines line-by-line alternation no alternation region change position #1 only first lines are used region change postion #0 no alternation only first lines are used when the vtpalt register is low (no alternation), only the first lines are used. figure 23. use of line alteration in vertical sequencing v1 v2 use f irst v sequences v3 v4 hd us e second v sequences use f irst v sequences sequences may be alternated within a region by using the sptrfirst and sptrsecond registers. figure 24. example of line alteration within a region
rev. a e22e ad9891/ad9895 second vertical sequence during vsg lines most ccds require additional vertical timing during the sensor gate line. the ad9891/ad9895 supports the option to output a second set of sequences for v1 ? v4 during the line when the sen- sor gates vsg1 ? vsg4 are active. figure 25 shows a typical vsg line, which includes two separate sets of vertical sequences on v1 ? v4. the sequences at the start of the line are the same as those generated in the previous line. but the second sequence only occurs in the line where the vsg signals are active. to select the sequences used for the second sequence, the registers in table xi are used. to enable the second set of sequences during the vsg line, the vtp_sglinemode is set high. as with the standard vertical regions, each v1 ? v4 output has an indi- vidual start position, programmed in the vxs tart_sgline registers. each v1 ? v4 output can select from the pool of 12 unique sequences using individual sequence pointer registers, vxsptr_sgline. also, any sequence may be inverted for a particular v1 ? v4 output by using the vxinv_sgline registers. vertical sweep mode operation the ad9891/ad9895 contains a special mode of vertical timing operation called sweep mode. this mode is used to generate a large number of repetitive pulses that span across multiple hd lines. one example of where this mode may be needed is at the start of the ccd readout operation. at the end of the image exposure, but before the image is transferred by the sensor gate pulses, the vertical interline ccd registers should be ? clean ? of all charge. this can be accomplished by quickly shifting out any charge with a long series of pulses on the v1 ? v4 outputs. de- pending on the vertical resolution of the ccd, up to two or three thousand clock cycles will be needed to shift the charge out of each vertical ccd line. this operation will span across mul- tiple hd line lengths. normally, the ad9891/ad9895 sequences are contained within one hd line length. but when sweep mode is enabled, the hd boundaries will be ignored until the region is finished. to enable sweep mode within any region, program the appropriate sweep (0 ? 4) registers to high. figure 26 shows an example of the sweep mode operation. the number of vertical pulses needed will depend on the vertical resolution of the ccd. the v1 ? v4 output signals are generated using the individual vertical sequence registers (shown in table vii). a single pulse is created using the first, second, and third toggle positions, and then the number of repeats is set to the number of vertical shifts required by the ccd. the maximum number of repeats is 4096 in this mode, using the vtprep r egister. this produces a pulse train of the appropriate length. normally, the pulse train would be truncated at the end of the hd line length. but with sweep mode enabled for this region, the hd boundaries will be ignored. in figure 26, the sweep region occupies 23 hd lines. after the sweep mode region is completed, normal sequence operation will resume in the next region . table xi. second vertical sequence registers during sg lines register name length range description vtp_sglinemode 1b high/low to turn on second s equences during sg line, set = high vxstart_sgline 12b 0 ? 4095 pixel location sequence start position for each vx output for sg line sequence vxsptr_sgline 4b 0 ? 11 sequence # sequence pointer for vx output during second sg line sequence vxinv_sgline 1b high/low when high, the polarity of sequence vxsptrfirst is inverted x is the v-output from 1 ? 4.
rev. a ad9891/ad9895 e23e v1 v2 v3 v4 hd sens or gate line vsg1e vsgx 2nd group of v-sequences are output during vsg line figure 25. example of second sequences during sensor gate line vd v1ev4 hd region area 1: sweep region line 0 line 1 region area 0 region area 2 line 24 line 25 line 2 figure 26. example of sweep region for high speed vertical shift
rev. a e24e ad9891/ad9895 vertical multiplier mode to generate very wide vertical timing pulses, a vertical region may be configured into multiplier mode. this mode uses the vertical sequence registers in a slightly different manner. multiplier mode can be used to support unusual ccd timing requirements, such as vertical pulses that are wider than a single hd line length. the start polarity and toggle positions are still used in the same manner as the standard sequence generation, but the length is used differently. instead of using the pixel counter (hd counter) to specify the toggle position locations (vtptog1, 2, 3) of the sequence, vtp length (vtplen) is multiplied by the vtptog position to allow very long sequences to be generated. to calculate the exact toggle position, counted in pixels after the start position: multiplier toggle position vtptog vtplen = because the vtptog register is multiplied by vtplen , the resolution of the toggle position placement is reduced. if vtplen = 4, the toggle position accuracy is now reduced to 4-pixel steps instead of single pixel steps. table xii summa rizes how the individual vertical sequence registers are pro- grammed for multiplier mode operation. note that the bit ranges for the vtptog and vtprep registers differ from the normal operation shown in table vii. in multiplier mode, the vtprep register should always be programmed to the same value as the highest toggle position register. the example shown in figure 27 illustrates this operation. the first toggle position is 2 and the second toggle position is 9. in nonmultiplier mode, this would cause the v-sequence to toggle at pixel 2 and then pixel 9 within a single hd line. how- ever, now toggle positions are multiplied by the vtplen = 4, so the first toggle occurs at pixel count = 8, and the second toggle occurs at pixel count = 36. sweep mode should be enabled to allow the toggle positions to cross the hd line boundaries. frame transfer ccd mode the ad9891/ad9895 may also be configured for use with frame t ransfer ccds. in frame transfer ccd (ftccd) mode, an additional four vertical outputs are available for a total of eight outputs (v1 ? v8). in this case, v1 ? v4 are used for clock- ing the active image area, and v5 ? v8 are used for clocking the storage area. in ftccd mode, the sequences assigned to the v1 ? v4 outputs are duplicated at the v5 ? v8 outputs to allow the storage area to be clocked along with the image area. individual masking of the v1 ? v4 and v5 ? v8 outputs allows for vertical decimation techniques during transfer from the image to the storage area. the additional outputs v5 ? v8 are available on four of the sensor gate output pins, vsg1 ? vsg4. figure 28 shows an example of the eight v-clocks configured for use with a frame transfer ccd. v1ev4 hd vtplen multiplier mode vertical sequence properties: 1: start polarity (above: startpol = 0) 2: 1st, 2nd, and 3rd toggle positions (above: vtptog1 = 2, vtptog2 = 9) 3: length of vtp counter (above: vtplen = 4). this is the minimum resolution for toggle position changes. 4: toggle positions occur at location equal to (vtptog vtplen) 5: enable sweep region allows the counters to cross the hd boundaries 12 34 12341234123412341234123412 3412341234 start position of sequence is individually programmable for each v1ev4 output pixels 1 234 5678910111213141516171819202122232425262728293031323334353637383940 3 55 4 1 2 4 2 figure 27. example of multiplier region for wide vertical pulse timing table xii. multiplier mode and sequence register parameters register length range description multi 1b high/low high enables multiplier mode for each region 0 ? 4 vtppol 1b high/low starting polarity of vertical transfer pulse for each sequence 0 ? 11 vtptog1 12b 0 ? 4095 pixel location first toggle position for each sequence 0 ? 11 vtptog2 12b 0 ? 4095 pixel location second toggle position for each sequence 0 ? 11 vtptog3 12b 0 ? 4095 pixel location third toggle position for each sequence 0 ? 7 vtplen 10b 0 ? 1023 pixels ? multiplier ? factor for repetition counter vtprep 12b 0 ? 4096 should be programmed to the same value as the highest toggle position
rev. a ad9891/ad9895 e25e v1 v2 v1 uses sequence 0 v3 v4 hd v2 uses sequence 0 v3 uses sequence 1 v4 uses sequence 1 v5 v6 v5 uses sequence 0 v7 v8 v6 uses sequence 0 v7 uses sequence 1 v8 uses sequence 1 active image area storage area figure 28. example of frame transfer ccd mode using v1ev8 the frame transfer ccd also requires additional timing con trol when decimating the image for preview mode. the ad9891/ad9895 contain registers to independently stop the operation of the v5 ? v8 outputs while the v1 ? v4 outputs con- ti nue to r un or to stop the v1 ? v4 outputs, while the v5 ? v8 outputs remain opera tional. the freeze and resume regis- ters specify the pixel loca tions within each line of a region where the v1 ? v4 or v5 ? v8 clock out puts will start to hold their state, and where they will resume normal operation. freeze and resume can be used in any region during the frame readout. vertical sensor gate (shift gate) timing with an interline ccd, the vertical sensor gates (vsg) are used to transfer the pixel charges from the light-sensitive image area into the light-shielded vertical registers. when a mechanical shutter is not being used, this transfer will effectively end the exposure period during the image acquisition. from the light-shield vertical registers, the image is then read out line-by-line by using the vertical transfer pulses v1 ? v4 in conjunction with the high speed horizontal clocks. vd hd programmable settings for each sequence: 1: start polarity of pulse 3: 2nd toggle position 2: 1st toggle position 4: active line for vsg pulse within the field vsg1evsg8 4 12 3 figure 29. vertical sensor gate pulse placement table xiii. sensor gate register parameters register length range description sgpol 1b high/low sensor gate starting polarity for sequence 0 ? 3 sgtog1 12b 0 ? 4095 pixel location first toggle position for sequence 0 ? 11 sgtog2 12b 0 ? 4095 pixel location second toggle position for sequence 0 ? 11 sgactline 12b 0 ? 4095 pixel location line in field where vsg1 ? vsg8 are active sgsel 2b sequence 0 ? 3 selects sequence 0 ? 3 for vsg1 ? vsg8 sgmask 8b 8 individual bits masking for any of vsg1 ? vsg8 signals (0 = on, 1 = mask)
rev. a e26e ad9891/ad9895 table xiii contains the summary of the vsg registers. the ad9891/ad9895 has eight sg outputs, vsg1 ? vsg8. each of the outputs can be assigned to one of four programmed sequences by using the sgsel1 ? sgsel8 registers. each sequence is generated in the same manner as the individual vertical sequences, with a programmable start polarity (sgpol), first toggle position (sgtog1), and second t oggle position (sgtog2). the active line where the vsg1 ? vsg8 pulses occur is program- mable using the two sgactlin registers. additionally, any of the vsg1 ? vsg8 pulses may be individually disabled by using the sgmask register. the masking allows all of the differ- ent sg sequences to be preprogrammed and the appropriate pulses for odd or even fields can be masked. shutter timing control ccd image exposure time is controlled through use of the substrate clock signal (subck), which pulses the ccd substrate to clear out accumulated charge. the ad9891/ad9895 supports three types of electronic shuttering: normal shutter mode, high preci- sion shutter mode, and low speed shutter mode. along with the subck pulse placement, the ad9891/ad9895 can accommo- date different progressive and interlaced readout modes. additionally, the ad9 8 91/ad9895 provides output signals to control an external mechani cal shutter, strobe (flash), and the ccd bias for still mode readout (vsub). normal shutter mode figure 30 shows the vd and subck output for normal shut- ter mode. the subck will pulse once per line, and the total number of repetitions within the field is programmable. the pulse polarity, width, and line location is programmable using the subckpol, subck1tog1, and subck1tog2 regis- ters (see table xiv). the number of subck pulses per field is programmed in the subcknum register. as shown in figure 30, the subck pulses will always begin on the line after the sensor gates occur, specified by the sgactline register (addr x265 and a ddr x266). the subckpol, subck1tog, subck2tog, and subcknum registers are updated at the start of the line after the sensor gate line. all other shutter mode registers are up- dated with the majority of the ad9891/ad9895 ? s registers at the vd/hd falling edge. high precision shutter mode high precision shuttering is controlled in the same way as nor- mal shuttering but requires a second set of toggle registers. in this mode, the subck still pulses once per line, but the last subck in the field will have an additional subck pulse whose location is determined by the subck2tog1 and subck2tog2 registers (see figure 31). finer resolution of the exposure time is possible using this mode. leaving both subck2tog registers set to 4095 (x3f) will disable the high precision mode (default setting). low speed shutter mode for normal exposure times less than one field interval, the exposure register will be set to 0. exposure times greater than one field interval can be achieved by writing a value greater than zero to the exposure register. as shown in figure 32, this shutter mode will suppress the subck and vsg outputs for up to 4095 fields (vd periods). the vd and hd outputs may be suppressed during the exposure period by programming the vdhdoff register to 1. vd subck subck programmable settings: 1: pulse polarity using the subckpol register 2: number of pulses within the field using the subcknum register 3: pixel location of pulse within the line and pulse width programmed using subck1 toggle position registers t exp vsg1e vsg8 hd t exp figure 30. normal shutter mode vd subck notes 1. 2nd subck pulse is added in the last subck line. 2. location of 2nd pulse is fully programmable using the subck2 toggle position registers. vsg1e vsg8 hd t exp t exp figure 31. high precision shutter mode
rev. a ad9891/ad9895 e27e subck suppression normally, the subcks will begin to pulse on the line following the sensor gate line (vsg). with some ccds, the subcks need to be suppressed for one or more lines following the vsg line. the subcksuppress register allows for the suppression the subck pulses for up to 63 lines following the vsg line. readout after exposure a write to the exposure register will designate the number fields in the exposure time (t exp ) from 0 to 4095. after the exposure, the readout of the ccd data occurs. during readout, the subck output may need to be further suppressed until the readout is completed. the readout register specifies the number of additional fields after the exposure to continue the suppression of subck. readout can be programmed for zero to seven additional fields and should be preprogrammed at start-up, not at the same time as the exposure write. a typical interlaced ccd frame readout mode will generally require two additional fields of subck suppression (readout = 2). note that a write to the exposure register acts as a trigger for readout after the exposure is completed. if no write to the exposure register occurs, than the readout register will have no effect. see figure 35 for an example of triggering the exposure and subsequent readout. vsub control the ccd readout bias (vsub) can be programmed to accom- modate different ccds. figure 35 shows two different modes that are available. in mode 0, vsub goes active during the field of the last subck when the exposure begins. the on-position (rising edge in figure 35) is programmable to any line within the field. vsub will remain active until the end of the image readout. in mode 1, the vsub is not activated until the start of the readout. mshut and strobe control mshut and strobe operation is shown in figures 33, 34, and 35. table xv shows the registers parameters for control- ling the mshut and strobe outputs. the mshut output is switched on with the mshuton registers, and it will remain on until the location specified in the mshutoff registers. the location of mshutoff is fully programmable to anywhere within the exposure period, using the fd (field), ln (line), and px (pixel) registers. the strobe pulse is defined by the on and off positions. strobon_fd is the field in which the strobe is turned on, measured from the field con- taining the last subck before exposure begins. the strobon_ ln and strobon_px registers give the line and pixel positions with respect to strobon_fd. the strobe off position is programmable to any field, line, and pixel location with respect to the field of the last subck. vd subck notes 1. subck may be suppressed for multiple fields by programming the exposure register greater than zero. 2. above example uses exposure = 1. 3. vd/hd outputs may also be suppressed using the vdhdoff register = 1. t exp vsg1e vsg8 figure 32. low speed shutter mode using exposure register table xiv. electronic shutter mode register parameters register length range description subckpol * 1b high/low subck start polarity for subck1 and subck2 subck1tog1 * 12b 0 ? 4095 pixel location subck first toggle position subck1tog2 * 12b 0 ? 4095 pixel location subck second toggle position subck2tog1 * 12b 0 ? 4095 pixel location second subck first toggle position (for high precision mode) subck2tog2 * 12b 0 ? 4095 pixel location second subck second toggle position (for high precision mode) subcknum * 12b 0 ? 4095 # of pulses total number of subcks per field (at 1 pulse per line) subcksuppress * 6b 0 ? 63 # of pulses number of subck ? s to suppress after vsg line exposure 12b 0 ? 4095 # of fields number of fields to suppress to subck and vsg; triggers readout to occur after t exp vdhdoff 1b on/off disable vd/hd output during exposure (1 = on, 0 = off) readout 3b 0 ? 7 # of fields number of fields to suppress subck after exposure (for readout) * register is not vd/hd updated but is updated at the start of line after sensor gate line.
rev. a e28e ad9891/ad9895 vd subck mshut programmable settings: 1: active polarity 2: on-position is vd updated and may be switched on at any time 3: off-position can be programmed anywhere from the field of last subck until the field before readout t exp vsg1e vsg8 mshut 3 1 2 figure 33. mshut output programmability vd subck strobe programmable settings: 1: active polarity 2: on-position with respect to to field of last subck 3: off-position can be programmed anywhere during the exposure time t exp vsg1e vsg8 strobe 1 2 3 figure 34. strobe output programmability table xv. vsub, mshut, and strobe register parameters register length range description trigger 3b on/off for three signals 1-bit triggers for vsub[0], mshut[1], and strobe[2] vsubmode 1b high/low vsub mode (0 = mode 0, 1 = mode 1) (see figure 27) vsubkeepon 1b high/low sets vsub to stay active after readout when high vsubpol 1b high/low vsub active polarity vsubon 12b 0 ? 4095 line location vsub on position. active starting in any line of field. mshuton 1b on/off mshut signal enable (1 = active or ? open ? ) mshutonpos_ln 12b 0 ? 4095 line location mshut line location mshutonpos_ln 12b 0 ? 4095 pixel location mshuton pixel location mshutpol 1b high/low mshut active polarity mshutoff_fd 12b 0 ? 4095 field location field location to switch off mshut. (inactive or ? closed ? ) mshutoff_ln 12b 0 ? 4095 line location line location to switch off mshut. (inactive or ? closed ? ) mshutoff_px 12b 0 ? 4095 pixel location pixel location to switch off mshut. (inactive or ? closed ? ) strobpol 1b high/low strobe active polarity strobon_fd 12b 0 ? 4095 field location strobe on field location, with respect to last subck field strobon_ln 12b 0 ? 4095 line location strobe on line location strobon_px 12b 0 ? 4095 pixel location strobe on pixel location stroboff_fd 12b 0 ? 4095 field location strobe off field location, with respect to last subck field stroboff_ln 12b 0 ? 4095 line location strobe off location stroboff_px 12b 0 ? 4095 pixel location strobe off location
rev. a ad9891/ad9895 e29e vd subck t exp vsub mechanical shutter open closed mode 0 mode 1 mshut strobe serial writes open vsg image readout odd even figure 35. exposure and readout of interlaced frame example of exposure and readout of interlaced frame figure 35 shows the sequence of events for a typical exposure and readout operation using a mechanical shutter and strobe. the register values for the vsub, mshut, and strobe toggle positions may be previously loaded at any time, prior to triggering these functions. additional register writes are required to configure the vertical clock outputs, v1 ? v4, which are not described here. 0: write to the readout register (addr x281) to specify the number of fields to further suppress subck while the ccd data is readout. in this example, readout = 2. 1: write to the exposure register (addr x27d) to start the exposure and specify the number of fields to suppress subck and vsg outputs during exposure. in this example, exposure = 2. write to the trigger register (addr x280) to enable the strobe, mshut, and vsub signals. to trigger all three signals (as in figure 36) the register trigger = 7. write to the sgactline register (addr x265 and addr x266) and sgmask register (addr x26f and addr x270) to configure the sensor gates for odd field readout (interlaced ccd). 2: vd/hd falling edge will update the serial writes from 1. 3: if vsub mode = 0, vsub output turns on at the line specified in the vsubon register (addr x272 and addr x273). strobe output turns on at the location specified in the strobon registers (addr x294 to addr x299). 4: strobe output turns off at the location specified in the strobeoff registers (addr x29a to addr x29f). 5: mshut output turns off at the location specified in the mshutoff registers (addr x28d to addr x292). 6: write to the sgactline register (addr x253 and addr x254) and sgmask register to configure the sensor gates for even field readout. 7: vd/hd falling edge will update the serial writes from 6. 8: write to the sgactline register and sgmask register to reconfigure the sensor gates for draft/preview mode output. write to the mshuton register (addr x287) to reopen the mechanical shutter for draft/preview mode. 9: vd/hd falling edge will update the serial writes from 8. 10: vsg outputs returns to draft/preview mode timing. subck output resumes operation. mshut output returns to the on position (active or ? open ? ). vsub output returns to the off position (inactive).
rev. a e30e ad9891/ad9895 analog front end description and operation the ad9891/ad9895 afe signal processing chain is shown in figure 36. each processing step is essential in achieving a high quality image from the raw ccd pixel data. afe register de- tails are shown in table xxxi. dc restore to reduce the large dc offset of the ccd output signal, a dc- restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.5 v, to be compatible with the 3 v analog supply of the ad9891/ad9895. correlated double sampler the cds circuit samples each ccd pixel twice to extract the video information and reject low frequency noise. the tim ing shown in figure 10 illustrates how the two internally gener ated cds clocks, shp and shd, are used to sample the reference level and the data level, respectively, of the ccd signal. the p lacement of the shp and shd sampling edges is deter mined by the setting of the shpposloc and shdposloc registers located at addr 0xe9 and ad dr 0xea, respectively. placement of these two clock signals is critical in achieving the best performance from the ccd. input clamp a line-rate input clamping circuit is used to remove the ccd ? s optical black offset. this offset exists in the ccd ? s shielded black reference pixels. the ad9891/ad9895 remove this offset in the input stage to minimize the effect of a gain change on the system black level. another advantage of removing this offset at the input stage is to maximize system headroom. some area ccds have large black level offset voltages, which, if not cor- rected at the input stage, can significantly reduce the available headroom in the internal circuitry when higher vga gain set- tings are used. the input clamp is controlled by the clpdm signal, which is fully programmable (see horizontal clamping and blanking section). system timing examples are shown in the horizontal timing sequence example section. it is recommended that the clpdm pulse be used during valid ccd dark pixels. clpdm may be used during the optical black pixels, either together with clpob or separately. the clpdm pulse should be a minimum of 4 pixels wide. pxga the pxga provides separate gain adjustment for the individual color pixels. a programmable gain amplifier with four separate values, the pxga has the capability to ? multiplex ? its gain value on a pixel-to-pixel basis (see figure 37). this allows lower output color pixels to be gained up to match higher output color pixels. also, the pxga may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed. the four different gain values are switched according to the ? color s teering ? circuitry. seven different color steering modes for dif- ferent types of ccd color filter arrays are programmed in the ad9891/ad9895 afe ctlmode register, at addr 0x06 (s ee figures 39a ? 39 g for internal color steering timing). for 0db to 36db clpdm ccdin digital filter clpob dc restore optical black clamp 0.1 f adc vga 8-bit dac clamp level register 8 vga gain register 10 cds internal v ref 2v full scale e2db to +10db 10 or 12 precision timing generation 0.1 f 0.1 f byp1 byp2 shp shd pxga 1.5v output data latch 1.0 f 1.0 f reft refb dout phase v-h timing generation shp shd dout phase clpdm clpob pblk pblk 1.0v 2.0v dout 0.1 f byp3 input offset clamp figure 36. afe block diagram
rev. a ad9891/ad9895 e31e rr gb gb gr gr bb ccd: progressive bayer line0 gain0, gain1, gain0, gain1, ... rr gr gr gb gb bb line1 line2 gain2, gain3, gain2, gain3, ... gain0, gain1, gain0, gain1, ... mosaic separate color steering mode figure 38a. ccd color filter example: progressive scan line0 gain0, gain1, gain0, gain1, ... rr gr gr line1 line2 gain0, gain1, gain0, gain1, ... gain0, gain1, gain0, gain1, ... gb gb bb line0 gain2, gain3, gain2, gain3, ... line1 line2 gain2, gain3, gain2, gain3, ... gain2, gain3, gain2, gain3, ... mosaic interlaced color steering mode gb gb bb gb gb bb gb gb bb rr gr gr rr gr gr rr gr gr even field odd field ccd: interlaced bayer figure 38b. ccd color filter example: interlaced vd notes 1. vd falling edge will reset the pxga gain register steering to 0101 line. 2. hd falling edges will alternate the pxga gain register steering between 0101 and 2323 lines. 3. fld status is ignored. hd 00 00 00 0 0 0 11 11 11 11 22 33 22 33 x x pxga gain register fld odd field even field figure 39a. mosaic separate color steering mode vd notes 1. fld falling edge (start of odd field) will reset the pxga gain register steering to 0101 line. 2. fld rising edge (start of even field) will reset the pxga gain register steering to 2323 line. 3. hd falling edges will reset the pxga gain register steering to either 0 (fld = odd) or 2 (fld = even). hd 00 00 22 2 0 2 11 11 33 33 00 11 22 33 x x pxga gain register fld odd field even field figure 39b. mosaic interlaced color steering mode example, the mosaic separate steering mode accommodates the popular ? bayer ? arrangement of red, green, and blue filters (see figure 38a). the same bayer pattern can also be interlaced, and the mosaic interlaced mode should be used with this type of ccd (see figure 38b). the color steering performs the proper multiplex- ing of the r, g, and b gain values (loaded into the pxga gain registers) and is synchronized by the vertical (vd) and horizon- tal (hd) sync pulses. the pxga g ain for each of the four channels is variable from ? 2d b to +10 db, controlled in 64 steps through the serial interface. the pxga g ain curve is shown in figure 40. color steering control 4:1 mux 3 pxga steering mode selection 2 6 vd hd pxga gain registers control register bits d0:d2 shp/shd vga cds gain0 gain1 gain2 gain3 pxga figure 37. pxga block diagram
rev. a e32e ad9891/ad9895 vd notes 1. vd falling edge will reset the pxga gain steering to 0101 line. 2. hd falling edges will alternate the pxga gain steering between 0101 and 1212 lines. 3. all fields will have the same pxga gain steering pattern (fld status is ignored). hd 00 00 00 0 0 0 11 11 11 11 11 22 11 22 x x pxga gain register fld odd field even field figure 39c. mosaic repeat color steering mode vd notes 1. each line follows 012012 steering pattern. 2. vd and hd falling edges will reset the pxga gain register steering to gain register 0. 3. fld status is ignored. hd 02 02 02 0 0 2 10 10 10 10 02 10 02 10 x x pxga gain register fld odd field even field figure 39d. 3-color 1-color steering mode vd notes 1. vd falling edge will reset the pxga gain register steering to 012012 line. 2. hd falling edges will alternate the pxga gain register steering between 012012 and 210210 lines. 3. fld status is ignored. hd 02 02 02 0 0 2 10 10 10 10 20 12 20 12 x x pxga gain register fld odd field even field figure 39e. 3-color 2-color steering mode vd notes 1. each line follows 01230123 steering pattern. 2. vd and hd falling edges will reset the pxga gain register steering to gain register 0. 3. fld status is ignored. hd 02 02 02 0 0 2 13 13 13 13 02 13 02 13 x x pxga gain register fld odd field even field figure 39f. 4-color 1-color steering mode
rev. a ad9891/ad9895 e33e pxga gain register code 10 32 pxga gain e db 40 48 58 0 8 16 24 31 6 4 2 0 e2 e4 8 (100000) (011111) figure 40. pxga gain curve vg a gain register code 36 0 0 1023 127 vg a gain e db 255 383 511 639 767 895 30 24 18 12 6 figure 41. vga gain curve (pxga not included) variable gain amplifier the vga stage provides a gain range of 2 db to 36 db, pro- grammable with 10-bit resolution through the serial digital interface. combined with approximately 4 db from the pxga stage, the total gain range for the ad9891/ad9895 is 6 db to 40 db. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full-scale range of 2 v. when com- pared to 1 v full-scale systems (such as adi ? s ad9803), the equivalent gain range is 0 db to 34 db. the vga gain curve follows a ? linear-in-db ? characteristic. the exact vga gain can be calculated for any gain register value by using the equation: gain code =+ (. ) . 0 035 3 55 where the code range is 0 to 1023. pxga default gain is included. the gain accuracy specifications include the pxga gain of approximately 4 db, for a total gain range of 6 db to 40 db. optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccd ? s black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with a fixed black level reference selected by the user in the clamp level register. the clamp level is programmable in 256 steps, with a range between 0 lsb and 63.75 lsb in the ad9891 and be- tween 0 lsb and 255 lsb in the ad9895. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a d/a converter. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particu- lar applica tion. if external digital clamping is used during the post- processing, the ad9891/ad9895 optical black clamping may be disabled using bit d5 in the operation regis- ter (see serial interface timing and register listing sections). when the loop is disabled, the clamp level register may still be used to provide programmable offset adjustment. the optical black clamp is controlled by the clpob signal, which is fully programmable (see horizontal clamping and blanking section). system timing examples are shown in the horizontal timing sequence example section. the clpob pulse should be placed during the ccd ? s optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide. shorter pulsewidths may be used, but the ability to track low frequency variations in the black level will be reduced. a/d converter the ad9891 uses a high a performance 10-bit adc archi- tecture, optimized for high speed and low power, while the ad9895 uses a 12-bit adc architecture. differential n onlinearity (dnl) performance is typically better than 0.5 lsb for both products. the adc uses a 2 v input range. better noise performance results from using a larger adc full- scale range. vd notes 1. vd falling edge will reset the pxga gain register steering to 01230123 line. 2. hd falling edges will alternate the pxga gain register steering between 01230123 and 23012301 lines. 3. fld status is ignored. hd 02 02 02 0 0 2 13 13 13 13 20 31 20 31 x x pxga gain register fld odd field even field figure 39g. 4-color 2-color steering mode
rev. a e34e ad9891/ad9895 vdd (input) serial writes vd (output) 1 h odd field even field sync (input) digital outputs clocks active when out_cont register is updated at vd/hd edge h1/h3, rg, dclk h2/h4 t pwr cli (input) hd (output) 1 v figure 42. recommended power-up sequence and synchronization, master mode power-up and synchronization recommended power-up sequence for master mode when the ad9891/ad9895 are powered up, the following sequence is recommended (refer to figure 42 for each step). 1. turn on power supplies for the ad9891/ad9895. 2. apply the master clock input cli. 3. reset and initialize the internal ad9891/ad9895 registers. first, write a ? 1 ? to the sw_reset register (addr x017) followed by a ? 0 ? to the same register. next, write ? 110101 ? (53 decimal) to the initial1 register (addr x02b) followed by ? 000100 ? (4 decimal) to the intial2 register (addr x010). this sequence of writes must always be done in the proper order: addr x017 data 000001 addr x017 data 000000 addr x02b data 110101 addr x010 data 000100 4. configure the ad9891/ad9895 for master mode timing by writing a ? 1 ? to the master register (addr x0eb). 5. by default, the internal timing core is held in a reset state with tgcore_rstb register = ? 0. ? write a ? 1 ? to the tgcore_rstb register (addr x029) to start the internal timing core operation. 6. write a ? 1 ? to the preventupdate register (addr x01b). this will prevent any updating of the serial register data. 7. write a ? 1 ? to the syncenable register (addr x024). this will allow the external sync to be used. 8. write a ? 1 ? to the syncsuspend register (addr x026). this will cause the outputs to be suspended during the sync operation (see figure 43). 9. write to desired registers to configure high speed timing, horizontal timing, vertical timing, and shutter timing. 10. if sync is high at power-up, then bring sync input low. also, sync may be held low from power-up. 11. write a ? 1 ? to the out_cont register (addr x018). this will allow the outputs to become active after sync rising edge. 12. write a ? 0 ? to the preventupdate register (addr x01b). this will allow the serial information to be up- dated at the next vd/hd falling edge. 13. bring sync back high. this will cause the internal counters to reset to ? 0 ? and start vd/hd operation. vd/hd edge allows register updates to occur, including out_cont, which enables all clock outputs. sync during master mode operation the sync input may be used any time during operation to resync the ad9891/ad9895 counters with external timing, as shown in figure 43. the operation of the digital outputs may be suspended during the sync operation by setting the syncsuspend register (addr x026) to a ? 1. ? synchronization in slave mode when the ad9891/ad9895 is used in slave mode, the vd and hd inputs are used to synchronize the internal counters. fol- lowing a falling edge of vd, there will be a latency of eight master clock cycles (cli) after the falling edge of hd until the internal h-counter will be reset. the reset operation is shown in figure 44.
rev. a ad9891/ad9895 e35e vd hd notes 1. sync rising edge resets vd/hd and counters to zero. 2. sync polarity is programmable using syncpol register (addr x025). 3. during sync low, all internal counters are reset and vd/hd can be suspended using the syncsuspend register (addr x026). 4. if syncsuspend = 1, vertical clocks and h1eh2, rg are held at their default polarities. 5. if syncsuspend = 0, then all clock outputs continue to operate normally until sync reset edge. suspend sync h124, rg, v1ev4, vsg, subck figure 43. sync timing to synchronize ad989x with external timing vd notes 1. internal h-counter is reset 8 clock cycles after the hd falling edge. 2. pxga steering is synchronized with the reset of the internal h-counter (mosaic separate mode is shown). hd xx 000 1 12 xx 111 0 0 3 xx x11 00 x x pxga gain register cli 0123 45678910111213140123 023 xx xxxx x x x h-counter (p ixel counter) 3ns min 4 h-counter reset figure 44. external vd/hd and internal h-counter synchronization, slave mode power-down mode operation the ad9891/ad9895 contain three different power-down modes to optimize the overall power dissipation in a particular applica tion. bits [1:0] of the oprmode register control the power-down state of the device: opr_mode [1:0] = 00 = normal operation (full power) opr_mode[1:0] = 01 = power-down 1 mode opr_mode[1:0] = 10 = power-down 2 mode opr_mode[1:0] = 11 = power-down 3 mode (lowest overall power) table xvi summarizes the operation of each power-down mode. note that in any mode, the out_cont register takes priority over the power-down modes where the digital output states are concerned. power-down 3 mode has the lowest power consump- tion, and it even powers down the crystal oscillator circuit between cli and clo. thus, if cli and clo are being used with a crystal to generate the master clock, this circuit will be powered down and there will be no clock signal. when returning from power-down 3 m ode to normal operation, the timing core must be reset at least 500 ms after the opr_mode register is writ ten to. this will allow sufficient time for the crystal circuit to settle.
rev. a e36e ad9891/ad9895 table xvi. power-down mode operation i/o block out_cont== low 1 power-down 1 1 power-down 2 1, 2 power-down 3 1, 3, 4 afe on off off off timing core on on off off clo oscillator on on on off v1 low low low low v2 low low low low v3 high high high low v4 high high high low vsg1 high high high low vsg2 high high high low vsg3 high high high low vsg4 high high high low vsg5 high high high low vsg6 high high high low vsg7 high high high low vsg8 high high high low subck high high high low vsub low low low low mshut low low low low strobe low low low low h1 low low low (3.5 ma) hi-z h2 high high high (3.5 ma) hi-z h3 low low low (3.5 ma) hi-z h4 high high high (3.5 ma) hi-z rg low low low (3.5 ma) hi-z ld/fd low low low low clpob/ high high high low pblk vd vdhdpol running vdhdpol low hd vdhdpol running vdhdpol low dclk low running low low clo running running running high dout low low low low notes 1 first column represents the defaults when out_cont==lo (out_cont takes precedence). power-down 1, 2, and 3 are direct decodes of the opr mode register bits [1:0]. these polarities assume out_cont==hi. 2 power-down 2 will set h[1,2,3,4]drv and rgdrv to 3 ? h1 (3.5 ma). power -down 3 will three-state the h and rg clocks (set h[1,2,3,4]drv and rgdrv to 3 ? h0). 3 both the timing core and the clo oscillator will be powered down in power-down 3. 4 to exit power-down 3, first write a 2 ? b00 to oprmode[1:0] (will wake up the oscillator and the timing core), then reset the timing core after ~500 s to guarantee lock.
rev. a ad9891/ad9895 e37e v h use se quence 2 use se quence 3 se quence 2 (optional) h orizontal ccd register e ffective image area 28 dummy pixels 48 ob pixels 4 ob pixels 10 vertical ob lines 2 vertical ob lines figure 45. example ccd configuration vertical shift vert shift se quence 1: vertical blanking ccdin shp shd h1/h3 h2/h4 hblk pblk clpob clpdm dummy invalid pixels invalid pix clpdm pulse may be used during horizontal dummy pixels if the h-clocks are used during vertical blanking. figure 46. horizontal sequences during vertical blanking horizontal timing sequence example figure 45 shows an example ccd layout. the horizontal regis- ter contains 28 dummy pixels that will occur on each line clocked from the ccd. in the vertical direction, there are 10 optical black (ob) lines at the front of the readout and two at the back of the readout. the horizontal direction has four ob pixels in the front and 48 in the back. to configure the ad9891/ad9895 horizontal signals for this ccd, three sequences can be used. figure 46 shows the first sequence to be used during vertical blanking. during this time, there are no valid ob pixels from the sensor, so the clpob and clpdm signals are not used. in some cases, if the horizontal clocks are used during this time, the clpdm signal may be used to keep the ad9891/ad9895 ? s input clamp partially settled. pblk may be enabled during this time because no valid data is available. figure 47 shows the recommended sequence for the vertical ob interval. the clamp signals are used across the whole lines in order to stabilize the clamp loops of the ad9891/ad9895. figure 48 shows the recommended sequence for the effective pixel readout. the 48 ob pixels at the end of each line are used for the clpob and clpdm signals.
rev. a e38e ad9891/ad9895 vertical shift vert shift sequence 2: vertical optical black lines ccdin shp shd h1/h3 h2/h4 hblk pblk clpob clpdm optical black dummy optical black figure 47. horizontal sequences during vertical optical black pixels vertical shift vert shift sequence 3: effective pixel lines ccdin shp shd h1/h3 h2/h4 hblk pblk clpob clpdm optical black dummy effective pixels ob optical black figure 48. horizontal sequences during effective pixels
rev. a ad9891/ad9895 e39e vertical timing example figure 49 shows an example ccd timing chart for an interlaced readout. each field can be broken down into four separate region areas. the vertical region c hange positions (rcps) will set the line boundaries for each region area, and the region pointers will assign a unique region to each region area. region area 0 is a high speed vertical shift region. sweep mode can be used to generate this timing operation, with the desired number of high speed vertical pulses needed to ? clean ? the charge from the ccd ? s vertical registers. region area 1 consists of only two lines and uses standard single line vertical shift timing. the timing of this region area will be the same as the timing in region area 3. region area 2 is the sensor gate line, where the vsg pulses trans- fer the image into the vertical ccd registers. this region will require the use of the second vertical sequence for sg lines. region area 3 also uses the standard single line vertical shift timing, the same timing as region area 1. in summary, three unique regions are required to support the four r egion areas, since region areas 1 and 3 use the same timing. some of the timing parameters will need to be adjusted to read out the second field, such as the sensor gate pulse and line location. vd hd v1/vsg1 v2 v3/vsg2 v4 subck mshut vs ub ccd out exposure period ( t exp ) interlaced readout period region area 1 region area 2 region area 0 region area 3 1 3 5 7 9 11 ne3 ne1 open close 2 4 6 8 10 12 ne2 n open 13 15 17 19 14 16 18 20 figure 49. vertical timing example?separate regions
rev. a e40e ad9891/ad9895 circuit layout information the ad9891/ad9895 typical circuit connection is shown in figure 50. note that pins e1 and e2 will be no connects when using the ad9891. the pcb layout is critical in achieving good image quality from the ad989x products. all of the supply pins, particularly the avdd1, tcvdd, rgvdd, and hvdd sup- plies, must be decoupled to ground with good quality high frequency chip capacitors. the decoupling capacitors should be located as close as possible to the supply pins and should have a very low im pedance path to a continuous ground plane. there should also be a 4.7 f or larger value bypass capacitor for each main supply ? avdd, rgvdd, hvdd, and drvdd ? although this is not necessary for each individual pin. in most applications, it is easier to share the supply for rgvdd and hvdd, which may be done as long as the individual supply pins are separately bypassed. a separate 3 v supply may also be used for drvdd, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. a separate ground for drvss is not recommended. the analog bypass pins (byp1 ? 3, vrb, vrt) should also be carefully decoupled to ground as close as possible to their re- spective pins. the analog input (ccdin) capacitor should also be located close to the pin. the h1 ? h4 and rg traces should be designed to have low inductance to avoid excessive distortion of the signals. heavier traces are recommended because of the large transient current demand on h1 ? h4 by the ccd. if possible, physically locating the ad9891/ad9895 closer to the ccd will reduce the induc- tance on these lines. as always, the routing path should be as direct as possible from the ad9891/ad9895 to the ccd. the ad9891/ad9895 also contains an on-chip oscillator for driving an external crystal. figure 51 shows an example appli- cation using a typical 18 mhz crystal. for the exact values of the external resistors and capacitors, it is best to consult with the crystal manufacturer ? s data sheet. 20pf c10 20pf 500 1m cli clo ad9891/ad9895 18mhz xtal figure 51. crystal driver application d0(lsb) d2 d1 hd dvdd dvss vd sync clpob/pblk ld/fd strobe mshut sck sdi sl dclk v4 vsg1/v5 vsg2/v6 vsg3/v7 vsg4/v8 vsg5 vsg6 vsg7 vsg8 h1 h2 hvss top view (not to scale) ad9895 reft refb avss2 avdd2 byp3 ccdin byp2 byp1 avss1 avdd1 tcvdd tcvss d3 d4 d5 d6 d7 d8 d9 d10 ( msb) d11 drvdd drvss vsub 3v analog supply output from ccd 10 data outputs subck v1 v2 v3 line/field/clamp sync to asic/dsp 3v analog supply external sync from asic/dsp 5 3 serial interface to asic or dsp to strobe circuit to mechanical shutter circuit 3v analog supply cli clo rgvdd rg 5v rg supply master clock input hvdd h3 h4 rgvss 9 v1ev4, vsg1evsg4, subck to v-driver vsub to ccd 5v h1eh4 supply rg, h1eh4 to ccd 5 + + + f1 g2 g1 h2 h1 j2 j1 k2 k1 k3 k4 j3 j4 k5 j5 k6 j6 k7 j7 k8 j8 k9 j9 k10 j10 h10 h9 g9 g10 f10 f9 e9 a5 a6 b6 b7 a7 a8 b8 a9 b9 a10 b10 c9 c10 d10 e10 d9 f2 e1 e2 d1 b1 a2 b2 a1 c1 d2 c2 b3 a3 b4 a4 b5 3v driver supply 4.7 f + 0.1 f 0.1 f 4.7 f 0.1 f 4.7 f 4.7 f 1 f 1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f figure 50. ad9891/ad9895 typical circuit configuration
rev. a ad9891/ad9895 e41e serial interface timing all of the internal registers of the ad9891/ad9895 are accessed through a 3-wire serial interface. each register consists of a 10-bit address and a 6-bit data-word. both the 10-bit address and 6-bit data-word are written starting with the lsb. to write to each register, a 16-bit operation is required, as shown in figure 52. although many registers are less than six bits wide, all six bits must be written to for each register. if the register is only two bits wide, then the upper four bits are don ? t cares and can be filled with 0s during the serial write operation. if less than six bits are written, the register will not be updated with new data. because of the large number of registers in the ad9891/ad9895, fig ure 53 shows a more efficient way to write to the registers, u si ng th e ad9891/ad9895 ? s address auto-increment capability. using this method, the lowest desired address is written first, fol- lowed by multiple 6- bit data-words. each new 6-bit data-word will auto matically be writ ten to the next highest register address. by eliminating the need for each 10-bit address to be w ritten, faster register loading is accomplished. address auto-incre- ment may be used starting with any register location and may be used to write to as few as two registers or as many as the entire register space. notes about accessing a double-wide register there are many double-wide registers in the ad9891/ ad9895. these registers are configured into two consecutive 6-bit registers with the least significant six bits located in the lower of the two addresses and the remaining most significant bits located in the higher of the two addresses. for example, the six lsbs of the oprmode register, oprmode[5:0], are located at addr 0x00. the most significant six bits of the oprmode register, oprmode[11:6], are located at addr 0x1. the following rules must be followed when access- ing double-wide registers: 1. when accessing a double-wide register, both addresses must be written to. 2. the lower of the two consecutive addresses for the double- wide register must be written to first. in the example of the oprmode register, the contents of addr 0x00 must be written first followed by the contents of addr 0x01. the register will be internally updated after the completion of the write to register 0x01, either at the next sl rising edge or the next vd/hd falling edge depending on the register. 3. a single write to the lower of the two consecutive addresses of a double-wide register that is not followed by a write to the higher address of the registers is not supported. this will not update the register. 4. a single write to the higher of the two consecutive addresses of a double-wide register that is not preceded by a write to the lower of the two addresses is not supported. although the write to the higher address will update the full double- wide register, the lower six bits of the register will be written with an indeterminate value if the lower address was not written to first. sdata a0 a1 a2 a4 a5 a6 a7 a8 a9 d0 d1 d2 d3 d4 d5 sck sl a3 notes sdata bits are latched on sck rising edges. each internal register is preloaded with new data at sl rising edge. new data is updated at either the sl rising edge or at the hd falling edge after the next vd falling edge. vd/hd update position may be delayed to any hd falling edge in the field using the update register. t dh t ls t lh t ds vd sl updated vd/hd updated hd figure 52. serial write operation sdata a0 a1 a2 a4 a5 a6 a7 a8 a9 d0 d1 d2 d3 d4 d5 a3 d0 d1 d2 d3 d4 d5 d0 data for starting re gister address data for next re gister address sck sl notes multiple sequential registers may be loaded continuously. the first (lowest address) register address is written followed by multiple 6-bit data-words. the address will automatically increment with each 6-bit data-word. sl is held low until the last desired register has been loaded. new data is updated at either the sl rising edge or at the hd falling edge after the next vd falling edge. figure 53. continuous serial write operation
rev. a e42e ad9891/ad9895 table xviii. sg-line updated registers register description subckpol subck start polarity subck1tog1 subck first toggle position subck1tog2 subck second toggle position subck2tog1 second subck first toggle position subck2tog2 second subck s econd toggle position subcknum total number of subcks per field subcksuppress number of subcks to suppress after vsg line notes on register listing 1. registers larger than six bits occupy two adjacent addresses. when writing to these registers, the lower address contain- ing the least significant data bits should be written to first. the data for both addresses should be written to avoid corruption of register data. 2. all addresses and default values are expressed in hexadecimal. 3. all registers are vd/hd updated as shown in figure 52, ex cept f or the registers indicated in table xvii , which are sl updated. 4. the registers indicated in table xviii are not updated by sl or vd/hd, but are updated at the hd line following the vsg line. table xvii. sl-updated register register description oprmode afe operation modes ctlmode afe c ontrol modes sw_reset softw are reset bit readback enables serial register readback mode fieldval r esets internal field pulse. h1hblkretime retimes the h1 hblk to internal clock h3hblkretime retimes the h3 hblk to internal clock syncenable e xternal synchronization enable syncpol e xternal sync active polarity syncsuspend s ync suspend while active tg_core rstb reset bar signal for internal tg core fftranccd fram e transfer ccd mode h12pol h1/h2 polarity control h1posloc h1 positive edge location h1negloc h1 negative edge location h34pol h3/h4 polarity control h3posloc h3 positive edge location h3negloc h3 negative edge location h1drv h1 drive current h2drv h2 drive current h3drv h3 drive current h4drv h4 drive current rgpol rg polarity rgposloc rg positive edge location rgnegloc rg n egative edge location shploc shp sample location shdloc shd sample location master vd/hd m aster/slave timing mode vdhdpol vd/hd a ctive polarity single_clamp sets clpdm = clpob dout_delay sets the output delay of dout osc_pwrdown powers down the clo oscillator vdhdpol vd/hd a ctive polarity
rev. a ad9891/ad9895 e43e table xix. afe register map bit default address content width value register name register description 00 [5:0] 6 10 oprmode[5:0] afe operation mode (see table xxxi.) 01 [1:0] 2 00 oprmode[7:6] 02 [5:0] 6 05 ccdgain [5:0] vga g ain (defaults to 2 db) 03 [3:0] 4 01 ccdgain[9:6] 04 [5:0] 6 00 refblack[5:0] b lack clamp level 05 [1:0] 2 02 refblack[7:6] 06 [5: 0] 60 0 ctlmode control mode (see table xxxi.) 07 [5:0] 6 00 pxga gain0 pxga color 0 gain 08 [5:0] 6 00 pxga gain1 pxga color 1 gain 09 [5:0] 6 00 pxga gain2 pxga color 2 gain 0a [5:0] 6 00 pxga gain3 pxga color 3 gain table xx. miscellaneous/extra register map bit default address content width value register name register description 010 [5:0] 6 00 intial2 see power-up sequence. should be set to ? 4. ? 017 [0] 1 00 sw_reset software reset (1 = reset all registers to default) 018 [0] 1 00 out_cont output control (0 = make all outputs dc inactive) 019 [5:0] 6 00 update[5:0] serial data update control. sets the line (hd) within the field for the serial data update to occur. 01a [5:0] 6 00 update[11:6] 01b [0] 1 00 preventupdate prevents the update of the vd updated registers 01c [0] 1 00 readback serial interface readback enable 01d [5:0] 6 00 doutphase dout phase control 01e [0] 1 00 dclkmode dclk mode (0 = dclk tracks dout phase, 1 = dclk is clo, i.e., cli inverse) 01f [0] 1 00 clidivide divide cli input clock by 2 020 [0] 1 00 disablerestore disable ccdin dc restore circuit during pblk (1 = disable) 021 [0] 1 01 fieldval reset internal field pulse value (0 = next field odd, 1 = next field even) 022 [0] 1 00 h1hblkretime re-time h1/h2 hblk to internal h1 clock 023 [0] 1 00 h3hblkretime re-time h3/h4 hblk to internal h3 clock 024 [0] 1 00 syncenable external synchronization enable (1 = enable) 025 [0] 1 00 syncpol sync active polarity (0 = active low) 026 [0] 1 00 syncsuspend suspend clocks during sync active (1 = suspend) 027 [0] 1 00 outputld assign ld/fd output (0 = fd, 1 = ld) 028 [0] 1 00 outputpblk assign clpob/pblk output (0 = clpob, 1 = pblk) 029 [0] 1 00 tgcore_rstb tg core reset_bar (0 = hold tg core in reset, 1 = resume operation) 02a [0] 1 00 ftranccd frame transfer ccd mode (1 = vsg1 ? vsg4 become v5 ? v8 out) 02b [5:0] 6 00 intial1 see power-up sequence. should be set to ? 53. ? 031 [0] 1 01 single_clamp clpdm = clpob when set to 1 (only clpob registers used). 032 [1:0] 2 02 dout_delay delay from dclk to dout (0 = no delay, 1= 4 ns, 2 = 8 ns, 3 = 12 ns) 033 [0] 1 01 osc_pwrdown clo oscillator power-down (0 = oscillator is powered down)
rev. a e44e ad9891/ad9895 table xxi. clpdm/clpob shared register map bit default address content width value register name register description 064 0 00 clpscp0 clpob/dm sequence-change position #0 (hard-coded to 0) 065 [5:0] 6 3f clpscp1[5:0] clpob/clpdm sequence-change position #1 066 [5:0] 6 3f clpscp1[11:6] 067 [5:0] 6 3f clpscp2[5:0] clpob/clpdm sequence-change position #2 068 [5:0] 6 3f clpscp2[11:6] 069 [5:0] 6 3f clpscp3[5:0] clpob/clpdm sequence-change position #3 06a [5:0] 6 3f clpscp3[11:6] 06b [5:0] 6 3f clpmask0[5:0] clpob/clpdm masking line #0 06c [5:0] 6 3f clpmask0[11:6] 06d [5:0] 6 3f clpmask1[5:0] clpob/clpdm masking line #1 06e [5:0] 6 3f clpmask1[11:6] 06f [5:0] 6 3f clpma sk2[5:0] clpob/clp dm masking line #2 070 [5:0] 6 3f clpmask2[11:6] 071 [5:0] 6 3f clpmask3[5:0] clpob/clpdm masking line #3 072 [5:0] 6 3f clpmask3[11:6] 073 [5:0] 6 3f clpmask4[5:0] clpob/clpdm masking line #4 074 [5:0] 6 3f clpmask4[11:6] table xxii. clpdm register map bit default address content width value register name register description 075 [0] 1 01 clpdmspol0 sequence #0: start polarity for clpdm 076 [5:0] 6 2e clpdmt og1_0[5:0] sequence #0: toggle position 1 for clpdm 077 [5:0] 6 00 clpdmtog1_0[11:6] 078 [5:0] 6 06 clpdmt og2_0[5:0] sequence #0: toggle position 2 for clpdm 079 [5:0] 6 03 clpdmtog2_0[11:6] 07a [0] 1 00 clpdmspol 1 sequence #1: start polarity for clpdm 07b [5:0] 6 3f clpdmt og1_1[5:0] sequence #1: toggle position 1 for clpdm 07c [5:0] 6 3f clpdmtog1_1[11:6] 07 d [5:0] 6 3f clpdmt og2_1[5:0] sequence #1: toggle position 2 for clpdm 07e [5:0] 6 3f clpdmtog2_1[11:6] 07f [0] 1 00 clpdmspol 2 sequence #2: start polarity for clpdm 080 [5:0] 6 3f clpdmt og1_2[5:0] sequence #2: toggle position 1 for clpdm 081 [5:0] 6 3f clpdmtog1_2[11:6] 082 [5:0] 6 3f clpdmt og2_2[5:0] sequence #2: toggle position 2 for clpdm 083 [5:0] 6 3f clpdmtog2_2[11:6] 084 [0] 1 00 clpdmspol 3 sequence #3: start polarity for clpdm 085 [5:0] 6 3f clpdmt og1_3[5:0] sequence #3: toggle position 1 for clpdm 086 [5:0] 6 3f clpdmtog1_3[11:6] 087 [5:0] 6 3f clpdmt og2_3[5:0] sequence #3: toggle position 2 for clpdm 088 [5:0] 6 3f clpdmtog2_3[11:6] 089 [1:0] 2 00 clpdmsptr0 clpdm sequence pointer for region #0 08a [1:0] 2 00 clpdmsptr1 clpdm sequence pointer for region #1 08b [1:0] 2 00 clpdmsptr2 clpdm sequence pointer for region #2 08c [1:0] 2 00 clpdmsptr 3 clpdm sequence pointer for region #3
rev. a ad9891/ad9895 e45e table xxiii. clpob register map bit default address content width value register name register description 08d [0] 1 01 clpobpol0 sequence #0: start polarity for clpob 08e [5:0] 6 0a clpobtog 1_0[5:0] sequ ence #0: toggle position 1 for clpob 08f [5:0] 6 00 clpobtog1_0[11:6] 090 [5:0] 6 2f clpobtog 2_0[5:0] sequ ence #0: toggle position 2 for clpob 091 [5:0] 6 00 clpobtog2_0[11:6] 092 [0] 1 00 clpobpol 1 sequence #1: start polarity for clpob 093 [5:0] 6 3f clpobtog 1_1[5:0] sequ ence #1: toggle position 1 for clpob 094 [5:0] 6 3f clpobtog1_1[11:6] 095 [5:0] 6 3f clpobtog 2_1[5:0] sequ ence #1: toggle position 2 for clpob 096 [5:0] 6 3f clpobtog2_1[11:6] 097 [0] 1 00 clpobpol 2 sequence #2: start polarity for clpob 098 [5:0] 6 3f clpobtog 1_2[5:0] sequ ence #2: toggle position 1 for clpob 099 [5:0] 6 3f clpobtog1_2[11:6] 09a [5:0] 6 3f clpobtog 2_2[5:0] sequ ence #2: toggle position 2 for clpob 09b [5:0] 6 3f clpobtog2_2[11:6] 09c [0] 10 0c lpo bs po l3 sequence #3: start polarity for clpob 09d [5:0] 6 3f clpobtog 1_3[5:0] sequ ence #3: toggle position 1 for clpob 09e [5:0] 6 3f clpobtog1_3[11:6] 09f [5:0] 6 3f clpobtog2_3[5:0] sequence #3: toggle position 2 for clpob 0a0 [5:0] 6 3f clpobtog2_3[11:6] 0a1 [1:0] 2 00 clpobsptr0 clp ob sequence pointer for region #0 0a2 [1:0] 2 00 clpobsptr1 clp ob sequence pointer for region #1 0a3 [1:0] 2 00 clpobsptr2 clp ob sequence pointer for region #2 0a4 [1:0] 2 00 clpobsptr3 clp ob sequence pointer for region #3 table xxiv. hblk register map * bit default address content width value register name register description 0a5 [0] 1 01 hblkmask_h1_0 sequence #0: h1 masking polarity for hblk 0a6 [0] 1 01 hblkmask_h3_0 sequ ence #0: h3 masking polarity for hblk 0a7 [5:0] 6 34 hblktog 1_0[5:0] sequ ence #0: toggle position 1 for hblk 0a8 [5:0] 6 00 hblktog1_0[11:6] 0a9 [5:0] 6 2c hblktog 2_0[5:0] sequ ence #0: toggle position 2 for hblk 0aa [5:0] 6 02 hblktog2_0[11:6] 0ab [0] 1 00 hblkmask_h1_1 sequence #1: h1 masking polarity for hblk 0ac [0] 1 00 hblkmask_h3_1 sequence #1: h3 masking polarity for hblk 0ad [5:0] 6 3f hblktog 1_1[5:0] sequ ence #1: toggle position 1 for hblk 0ae [5:0] 6 3f hblktog1_1[11:6] 0af [5:0] 6 3f hblktog2_1[5:0] sequence #1: toggle position 2 for hblk 0b0 [5:0] 6 3f hblktog2_1[11:6] 0b1 [0] 1 00 hblkmask_h1_2 sequence #2: h1 masking polarity for hblk 0b2 [0] 1 00 hblkmask_h3_2 sequence #2: h3 masking polarity for hblk 0b3 [5:0] 6 3f hblktog 1_2[5:0] sequ ence #2: toggle position 1 for hblk 0b4 [5:0] 6 3f hblktog1_2[11:6] 0b5 [5:0] 6 3f hblktog 2_2[5:0] sequ ence #2: toggle position 2 for hblk 0b6 [5:0] 6 3f hblktog2_2[11:6] 0b7 [0] 1 00 hblkmask_h1_3 sequence #3: h1 masking polarity for hblk 0b8 [0] 1 00 hblkmask_h3_3 sequence #3: h3 masking polarity for hblk 0b9 [5:0] 6 3f hblktog 1_3[5:0] sequ ence #3: toggle position 1 for hblk 0ba [5:0] 6 3f hblktog1_3[11:6] 0bb [5:0] 6 3f hblktog 2_3[5:0] sequ ence #3: toggle position 2 for hblk 0bc [5:0] 6 3f hblktog2_3[11:6] * hblk sequence-change positions shared with the vertical transfer pulses.
rev. a e46e ad9891/ad9895 table xxv. pblk register map bit default address content width value register name register description 0bd [0] 1 00 pblkspol0 sequence #0: start polarity for pblk 0be [5:0] 6 10 pblktog 1_0[5:0] sequence #0: toggle position 1 for pblk 0bf [5:0] 6 03 pblktog1_0[11:6] 0c0 [5:0] 6 3f pblkbtog 2_0[5:0] sequence #0: toggle position 2 for pblk 0c1 [5:0] 6 3f pblkbtog2_0[11:6] 0c2 [0] 1 00 pblkspol1 sequence #1: start polarity for pblk 0c3 [5:0] 6 3f pblktog 1_1[5:0] sequence #1: toggle position 1 for pblk 0c4 [5:0] 6 3f pblktog1_1[11:6] 0c5 [5:0] 6 3f pblktog 2_1[5:0] sequence #1: toggle position 2 for pblk 0c6 [5:0] 6 3f pblktog2_1[11:6] 0c7 [0] 1 00 pblkspol2 sequence #2: start polarity for pblk 0c8 [5:0] 6 3f pblktog 1_2[5:0] sequence #2: toggle position 1 for pblk 0c9 [5:0] 6 3f pblktog1_2[11:6] 0ca [5:0] 6 3f pblktog 2_2[5:0] sequence #2: toggle position 2 for pblk 0cb [5:0] 6 3f pblktog2_2[11:6] 0cc [0] 1 00 pblkspol3 sequence #3: start polarity for pblk 0cd [5:0] 6 3f pblktog 1_3[5:0] sequence #3: toggle position 1 for pblk 0ce [5:0] 6 3f pblktog1_3[11:6] 0cf [5:0] 6 3f pblktog2_3[5:0] sequence #3: toggle position 2 for pblk 0d0 [5:0] 6 3f pblktog2_3[11:6] 00 0 pblkscp0 pblk sequence-change position #0 (hard-coded to 0) 0d1 [1:0] 2 00 pblksptr0 pblk sequence pointer for region #0 0d2 [5:0] 6 3f pblkscp1[5:0] pblk sequence-change position #1 0d3 [5:0] 6 3f pblkscp1[11:6] 0d4 [1:0] 2 00 pblksptr1 pblk sequence pointer for region #1 0d5 [5:0] 6 3f pblkscp2[5:0] pblk sequence-change position #2 0d6 [5:0] 6 3f pblkscp2[11:6] 0d7 [1:0] 2 00 pblksptr2 pblk sequence pointer for region #2 0d8 [5:0] 6 3f pblkscp3[5:0] pblk sequence-change position #3 0d9 [5:0] 6 3f pblkscp3[11:6] 0da [1:0] 2 00 pblksptr3 p blk sequence pointer for region #3 table xxvi. h1eh4, rg, shp, shd register map bit default address content width value register name register description 0db [0] 1 01 h12pol h1/h2 polarity control (0 = inversion, 1= no inversion) 0dc [5:0] 6 00 h1posloc h1 positive edge location 0dd [5:0] 6 20 h1negloc h1 negative edge location 0de [0] 1 01 h34pol h3/h4 polarity control (0 = inversion, 1= no inversion) 0df [5:0] 6 00 h3posloc h3 positive edge location 0e0 [5:0] 6 20 h3negloc h3 negative edge location 0e1 [2:0] 3 03 h1drv h1 drive strength (0 = off, 1 = 3.5 ma, 2= 7 ma, 3 = 10.5 ma, 4 = 14 ma, 5= 17.5 ma, 6 = 21 ma, 7 = 24.5 ma) 0e2 [2:0] 3 03 h2drv h2 drive strength 0e3 [2:0] 3 03 h3drv h3 drive strength 0e4 [2:0] 3 03 h4drv h4 drive strength 0e5 [0] 1 01 rgpol rg polarity control (0 = inversion, 1= no inversion) 0e6 [5:0] 6 00 rgposloc rg positive edge location oe7 [5:0] 6 10 rgnegloc rg negative edge location 0e8 [2:0] 3 02 rgdrv rg drive strength (0 = off, 1 = 3.5 ma, 2= 7 ma, 3 = 10.5 ma, 4 = 14 ma, 5= 17.5 ma, 6 = 21 ma, 7 = 24.5 ma) 0e9 [5:0] 6 24 shpposloc shp (positive) edge sampling location 0ea [5:0] 6 00 shdposloc shd (positive) edge sampling location
rev. a ad9891/ad9895 e47e table xxvii. hd/vd register map bit default address content width value register name register description 0eb [0] 1 00 master vd/hd master or slave timing (0 = slave, 1= master) 0ec [0] 10 0 vdhdpol vd/hd active polarity (0 = low active, 1= high active) 0ed [5:0] 6 09 vdrise vd rising e dge location (hd location in field) 0ee [5:0] 6 07 vdlen[5:0] vd field l ength (number of lines per field) 0e f [4:0] 6 04 vdlen[11:6] 0f0 [5:0] 6 33 hdrise[5:0] hd rising edge location (pixel location in line) 0f1 [5:0] 6 01 hdrise[11:6] 0f2 [5:0] 6 38 hdlastlen[5:0] hd last line length (number of pixels in last line of field) 0f3 [5:0] 6 11 hdlastlen[11:6] table xxviii. v1ev8 register map bit default address content width value register name register description 0f4 [0] 1 00 vtppol0 sequence #0: start polarity 0f5 [5:0] 6 05 vtptog1_0[5:0] sequence #0: toggle position 1 0f6 [5:0] 6 00 vtptog1_0[11:6] 0f7 [5:0] 6 12 vtptog2_0[5:0] sequence #0: toggle position 2 0f8 [5:0] 6 00 vtptog2_0[11:6] 0f9 [5:0] 6 3f vtptog3_0[5:0] sequence #0: toggle position 3 0fa [5:0] 6 3f vtptog3_0[11:6] 0fb [5: 0] 62 4 vtplen0[5:0] sequence # 0: total length 0fc [3:0] 4 00 vtplen0[9:6] 0fd [5:0] 6 03 vtprep0[5:0] sequence #0: repetitions 0fe [11:6] 6 00 vtprep0[11:6] 0ff [0] 10 0 vtppol1 sequence #1: start polarity 100 [5:0] 6 17 vtptog1_1[5:0] sequence #1: toggle position 1 101 [5:0] 6 00 vtptog1_1[11:6] 102 [5:0] 6 3f vtptog2_1[5:0] sequence #1: toggle position 2 103 [5:0] 6 3f vtptog2_1[11:6] 104 [5:0] 6 3f vtptog3_1[5:0] sequence #1: toggle position 3 105 [5:0] 6 3f vtptog3_1[11:6] 106 [5:0] 6 24 vtplen1[5:0] sequ ence #1: total length 107 [3:0] 4 00 vtplen1[9:6] 108 [5:0] 6 03 vtprep1[5: 0] sequence #1: repetitions 109 [11:6] 6 00 vtprep1[11:6] 10a [0] 1 01 vtppol2 sequence #2: start polarity 10b [5:0] 6 16 vtptog1_2[5:0] sequence #2: toggle position 1 10c [5:0] 6 02 vtptog1_2[11:6] 10d [5:0] 6 2c vtptog2_2[5:0] sequence #2: toggle position 2 10e [5:0] 6 04 vtptog2_2[11:6] 10f [5:0] 6 28 vtptog3_2[5:0] sequence #2: toggle position 3 110 [5:0] 6 05 vtptog3_2[11:6] 111 [5:0] 6 28 vtplen2[5:0] sequ ence #2: total length 112 [3:0] 4 05 vtplen2[9:6] 113 [5:0] 6 01 vtprep2[5: 0] sequence #2: repetitions 114 [11:6] 6 00 vtprep2[11:6] 115 [0] 1 01 vtppol3 sequence #3: start polarity 116 [5:0] 6 1a vtptog1_3[5:0] sequence #3: toggle position 1 117 [5:0] 6 01 vtptog1_3[11:6] 118 [5:0] 6 30 vtptog2_3[5:0] sequence #3: toggle position 2 119 [5:0] 6 03 vtptog2_3[11:6] 11a [5:0] 6 2c vtptog3_3[5:0] sequence #3: toggle position 3 11b [5:0] 6 04 vtptog3_3[11:6]
rev. a e48e ad9891/ad9895 table xxviii. v1ev8 register map (continued) bit default address content width value register name register description 11c [5:0] 6 2c vtplen3[5:0] sequence #3: total length 11d [3:0] 4 04 vtplen3[9:6] 11e [5:0] 6 01 vtprep3[ 5:0] sequence #3: repetitions 11f [11:6] 6 00 vtprep3[11:6] 120 [0] 1 00 vtppol4 sequence #4: start polarity 121 [5:0] 6 34 vtptog1_4[5: 0] sequence #4: toggle position 1 122 [5:0] 6 02 vtptog1_4[11:6] 123 [5:0] 6 0a vtptog2_4[5: 0] sequence #4: toggle position 2 124 [5:0] 6 05 vtptog2_4[11:6] 125 [5:0] 6 06 vtptog3_4[5: 0] sequence #4: toggle position 3 126 [5:0] 6 06 vtptog3_4[11:6] 127 [5:0] 6 06 vtplen4[5:0] sequence #4: total length 128 [3:0] 4 06 vtplen4[9:6] 129 [5:0] 6 01 vtprep4[ 5:0] sequence #4: repetitions 12a [11:6] 6 00 vtprep4[11:6] 12b [0] 1 00 vtppol5 sequence #5: start polarity 12c [5:0] 6 12 vtptog1_5[5: 0] sequence #5: toggle position 1 12d [5:0] 6 03 vtptog1_5[11:6] 12 e [5:0] 6 2c vtptog2_5[5:0] sequence #5: toggle position 2 12f [5:0] 6 04 vtptog2_5[11:6] 130 [5:0] 6 28 vtptog3_5[5:0] sequence #5: toggle position 3 131 [5:0] 6 05 vtptog3_5[11:6] 132 [5:0] 6 28 vtplen5[5:0] sequence #5: total length 133 [3:0] 4 05 vtplen5[9:6] 134 [5:0] 6 01 vtprep5[ 5:0] sequence #5: repetitions 135 [11:6] 6 00 vtprep5[11:6] 136 [0] 1 00 vtppol6 sequence #6: start polarity 137 [5:0] 6 3f vtptog1_6[5:0] sequence #6: toggle position 1 138 [5:0] 6 3f vtptog1_6[11:6] 139 [5:0] 6 3f vtptog2_6[5:0] sequence #6: toggle position 2 13a [5:0] 6 3f vtptog2_6[11:6] 13b [5:0] 6 3f vtptog3_6[5:0] sequence #6: toggle position 3 13c [5:0] 6 3f vtptog3_6[11:6] 13d [5:0] 6 00 vtplen6[5:0] sequence #6: total length 13e [3:0] 4 00 vtplen6[9:6] 13f [5:0] 6 00 vtprep6[5: 0] sequence #6: repetitions 140 [11:6] 6 00 vtprep6[11:6] 141 [0] 1 00 vtppol7 sequence #7: start polarity 142 [5:0] 6 3f vtptog1_7[5:0] sequence #7: toggle position 1 143 [5:0] 6 3f vtptog1_7[11:6] 144 [5:0] 6 3f vtptog2_7[5:0] sequence #7: toggle position 2 145 [5:0] 6 3f vtptog2_7[11:6] 146 [5:0] 6 3f vtptog3_7[5:0] sequence #7: toggle position 3 147 [5:0] 6 3f vtptog3_7[11:6] 148 [5:0] 6 00 vtplen7[5:0] sequence #7: total length 149 [3:0] 4 00 vtplen7[9:6] 14a [5:0] 6 00 vtprep7[ 5:0] sequence #7: repetitions 14b [11:6] 6 00 vtprep7[11:6] 14c [0] 10 0 vtppol8 sequence #8: start polarity 14d [5:0] 6 3f vtptog1_8[5:0] sequence #9: toggle position 1 14e [3:0] 4 3f vtptog1_8[9:6] 14f [5:0] 6 3f vtptog2_8[5:0] sequence #8: toggle position 2 150 [3:0] 4 3f vtptog2_8[9:6] 151 [5:0] 6 00 vtplen8[5:0] sequence #8: total length 152 [3:0] 4 00 vtplen8[9:6] 153 [5:0] 6 00 vtprep8 sequence #8: repetitions
rev. a ad9891/ad9895 e49e table xxviii. v1ev8 register map (continued) bit default address content width value register name register description 154 [0] 1 00 vtppol8 sequence #9: start polarity 155 [5:0] 6 3f vtptog1_9[5:0] sequence #9: toggle position 1 156 [3:0] 4 3f vtptog1_9[9:6] 157 [5:0] 6 3f vtptog2_9[5:0] sequence #9: toggle position 2 158 [3:0] 4 3f vtptog2_9[9:6] 159 [5:0] 6 00 vtplen9[5:0] s equence #9: total length 15a [3:0] 4 00 vtplen9[9:6] 15b [5:0] 6 00 vtprep9 sequence #9: repetitions 15c [0] 10 0 vtppol10 s equence #10: start polarity 15d [5:0] 6 3f vtptog1_10[5:0] s equence #10: toggle position 1 15e [3:0] 4 3f vtptog1_10[6:0] 15f [5:0] 6 3f vtptog2_10[5:0] s equence #10: toggle position 2 160 [3:0] 4 3f vtptog2_10[9:6] 161 [5:0] 6 00 vtplen10[5:0] s equence #10: total length 162 [3:0] 4 00 vtplen10[9:6] 163 [5:0] 6 00 vtprep10 sequence #10: repetitions 164 [0] 1 00 vtppol11 s equence #11: start polarity 165 [5:0] 6 3f vtptog1_11[5:0] s equence #11: toggle position 1 166 [3:0] 4 3f vtptog1_11[9:6] 167 [5:0] 6 3f vtptog2_11[5:0] s equence #11: toggle position 2 168 [3:0] 4 3f vtptog2_11[9:6] 169 [5:0] 6 00 vtplen11[5:0] s equence #11: total length 16a [3:0] 4 00 vtplen11[9:6] 16b [5:0] 6 00 vtprep11 sequence #11: repetitions 00 0 vtprcp0 v region-change position #0 (hard-coded to 0) 16c [2:0] 3 00 vtpregptr0 v region pointer for sequence-change position #0 16d [5:0] 6 3f vtprcp1[5:0] v region-change position #1 16e [5:0] 6 3f vtprcp1[11:6] 16f [2:0] 3 00 vtpregptr1 v region pointer for sequence-change position #1 170 [5:0] 6 3f vtprcp2[5:0] v region-change position #2 171 [5:0] 6 3f vtprcp2[11:6] 172 [2:0] 3 00 vtpregptr2 v region pointer for sequence-change position #2 173 [5:0] 6 3f vtprcp3[5:0] v region-change position #3 174 [5:0] 6 3f vtprcp3[11:6] 175 [2:0] 3 00 vtpregptr3 v region pointer for sequence-change position #3 176 [5:0] 6 3f vtprcp4[5:0] v region-change position #4 177 [5:0] 6 3f vtprcp4[11:6] 178 [2:0] 3 00 vtpregptr4 v region pointer for sequence-change position #4 179 [5:0] 6 3f vtprcp5[5:0] v region-change position #5 17a [5:0] 6 3f vtprcp5[11:6] 17b [2:0] 3 00 vtpregptr5 v region pointer for sequence-change position #5 17c [5:0] 6 3f vtprcp6[5:0] v region-change position #6 17d [5:0] 6 3f vtprcp6[11:6] 17e [2:0] 3 00 vtpregptr6 v region pointer for sequence-change position #6 17f [5:0] 6 3f vtprcp7[5:0] v region-change position #7 180 [5:0] 6 3f vtprcp7[11:6] 181 [2:0] 3 00 vtpregptr7 v region pointer for sequence-change position #7 182 [0] 1 00 sweep0 v sweep for region #0 183 [0] 1 00 multi0 v multiplier for region #0 184 [5:0] 6 30 hdlen0[5:0] region #0 hd line length 185 [5:0] 6 23 hdlen0[11:6] 186 [1:0] 2 00 hblksptr0 hblk sequence for region #0 187 [0] 1 00 vtpalt0 vtp sequence alternation for region #0 188 [3:0] 4 00 v1sptrfirst0 v1 s equence for region #0 (1st lines)
rev. a e50e ad9891/ad9895 table xxviii. v1ev8 register map (continued) bit default address content width value register name register description 189 [0] 1 00 v1invfirst0 v1 sequence inversion for region #0 (first lines) 18a [3:0] 4 00 v1sptrsecond0 v1 sequence for region #0 (second lines) 18b [0] 1 00 v1invsecond0 v1 sequence inversion for region #0 (second lines) 18c [5:0] 6 34 v4_7start4[5:0] v1 and v5 sequence start for region #0 18d [5:0] 6 00 v1_5start0[11:6] 18e [3:0] 4 00 v2sptrfirst0 v2 sequence for region #0 (first lines) 18f [0] 1 00 v2invfirst0 v2 sequence inversion for region #0 (first lines) 190 [3:0] 4 00 v2sptrsecond0 v2 sequence for region #0 (second lines) 191 [0] 1 00 v2invsecond0 v2 sequence inversion for region #0 (second lines) 192 [5:0] 6 3d v4_7start4[5:0] v2 and v6 sequence start for region #0 193 [5:0] 6 00 v2_6start0[11:6] 194 [3:0] 4 01 v3sptrfirst0 v3 sequence for region #0 (first lines) 195 [0] 1 00 v3invfirst0 v3 sequence inversion for region #0 (first lines) 196 [3:0] 4 00 v3sptrsecond0 v3 sequence for region #0 (second lines) 197 [0] 1 00 v3invsecond0 v3 sequence inversion for region #0 (second lines) 198 [5:0] 6 34 v4_7start4[5:0] v3 and v7 sequence start for region #0 199 [5:0] 6 00 v3_7start0[11:6] 19a [3:0] 4 01 v4sptrfirst0 v4 sequence for region #0 (first lines) 19b [0] 1 00 v4invfirst0 v4 sequence inversion for region #0 (first lines) 19c [3:0] 4 00 v4sptrsecond0 v4 sequence for region #0 (second lines) 19d [0] 1 00 v4invsecond0 v4 sequence inversion for region #0 (second lines) 19e [5:0] 6 3d v4_8start0[5:0] v4 and v8 sequence start for region #0 19f [5:0] 6 00 v4_8start0[11:6] 1a0 [5:0] 6 00 v1_4freeze0[5:0] v1 ? v4 freeze start position for region #0 1a1 [5:0] 6 00 v1_4freeze0[11:6] 1a2 [5:0] 6 00 v1_4resume0[5:0] v1 ? v4 resume start position for region #0 1a3 [5:0] 6 00 v1_4resume0[11:6] 1a4 [5:0] 6 00 v5_8freeze0[5:0] v5 ? v8 freeze start position for region #0 1a5 [5:0] 6 00 v5_8freeze0[11:6] 1a6 [5:0] 6 00 v5_8resume0[5:0] v5 ? v8 resume start position for region #0 1a7 [5:0] 6 00 v5_8resume0[11:6] 1a8 [0] 1 00 sweep1 v sweep for region #1 1a9 [0] 1 00 multi1 v multiplier for region #1 1aa [5:0] 6 3f hdlen1[5:0] region #1 hd line length 1ab [5:0] 6 3f hdlen1[11:6] 1ac [1:0] 2 00 hblksptr1 hbl k sequence for region #1 1ad [0] 1 00 vtpalt1 v sequence alternation for region #1 1ae [3:0] 4 00 v1sptrfirst1 v1 sequence for region #1 (first lines) 1af [0] 1 00 v1invfirst1 v1 sequence inversion for region #1 (first lines) 1b0 [3:0] 4 00 v1sptrsecond1 v1 sequence for region #1 (second lines) 1b1 [0] 1 00 v1invsecond1 v1 sequence inversion for region #1 (second lines) 1b2 [5:0] 6 00 v1_5start1[5:0] v1 and v5 sequence start for region #1 1b3 [5:0] 6 00 v1_5start1[11:6] 1b4 [3:0] 4 00 v2sptrfirst1 v2 sequence for region #1 (first lines) 1b5 [0] 1 00 v2invfirst1 v2 sequence inversion for region #1 (first lines) 1b6 [3:0] 4 00 v2sptrsecond1 v2 sequence for region #1 (second lines) 1b7 [0] 1 00 v2invsecond1 v2 sequence inversion for region #1 (second lines) 1b8 [5:0] 6 00 v2_6start1[5:0] v2 and v6 sequence start for region #1 1b9 [5:0] 6 00 v2_6start1[11:6] 1ba [3:0] 4 00 v3sptrfirst1 v3 sequence for region #1 (first lines) 1bb [0] 1 00 v3invfirst1 v3 sequence inversion for region #1 (first lines) 1bc [3:0] 4 00 v3sptrsecond1 v3 sequence for region #1 (second lines) 1bd [0] 1 00 v3invsecond1 v3 sequence inversion for region #1 (second lines) 1be [5:0] 6 00 v3_7start1[5:0] v3 and v7 sequence start for region #1
rev. a ad9891/ad9895 e51e table xxviii. v1ev8 register map (continued) bit default address content width value register name register description 1bf [5:0] 6 00 v3_7start1[11:6] 1c0 [3:0] 4 00 v4sptrfirst1 v4 sequence for region #1 (first lines) 1c 1 [0] 1 00 v4invfirst1 v4 sequence inversion for region #1 (first lines) 1c2 [3:0] 4 00 v4sptrsecond1 v4 sequence for region #1 (second lines) 1c3 [0] 1 00 v4invsecond1 v4 sequence inversion for region #1 (second lines) 1c4 [5:0] 6 00 v4_8start1[5:0] v4 and v8 sequence start for region #1 1c5 [5:0] 6 00 v4_8start1[11:6] 1c6 [5:0] 6 00 v1_4freeze1[5:0] v1 ? v4 freeze start position for region #1 1c7 [5:0] 6 00 v1_4freeze1[11:6] 1c8 [5:0] 6 00 v1_4resume1[5:0] v1 ? v4 resume start position for region #1 1c9 [5:0] 6 00 v1_4resume1[11:6] 1ca [5:0] 6 00 v5_8freeze1[5:0] v5 ? v8 freeze start position for region #1 1cb [5:0] 6 00 v5_8freeze1[11:6] 1cc [5:0] 6 00 v5_8resume1[5:0] v5 ? v8 resume start position for region #1 1cd [5:0] 6 00 v5_8resume1[11:6] 1ce [0] 1 00 sweep2 v sweep for region #2 1cf [0] 1 00 multi2 v m ultiplier for region #2 1d0 [5:0] 6 3f hdlen2[5:0] region #2 hd line length 1d1 [5:0] 6 3f hdlen2[11:6] 1d2 [1:0] 2 00 hblksptr2 hblk sequence for region #2 1d3 [0] 1 00 vtpalt2 v sequence alternation for region #2 1d4 [3:0] 4 00 v1sptrfirst2 v1 sequence for region #2 (first lines) 1d5 [0] 1 00 v1invfirst2 v1 sequence inversion for region #2 (first lines) 1d6 [3:0] 4 00 v1sptrsecond2 v1 sequence for region #2 (second lines) 1d7 [0] 1 00 v1invsecond2 v1 sequence inversion for region #2 (second lines) 1d8 [5:0] 6 00 v1_5start2[5:0] v1 and v5 sequence start for region #2 1d9 [5:0] 6 00 v1_5start2[11:6] 1da [3:0] 4 00 v2sptrfirst2 v2 sequence for region #2 (first lines) 1db [0] 1 00 v2invfirst2 v2 sequence inversion for region #2 (first lines) 1dc [3:0] 4 00 v2sptrsecond2 v2 sequence for region #2 (second lines) 1dd [0] 1 00 v2invsecond2 v2 sequence inversion for region #2 (second lines) 1de [5:0] 6 00 v2_6start2[5:0] v2 and v6 sequence start for region #2 1df [5:0] 6 00 v2_6start2[11:6] 1e0 [3:0] 4 00 v3sptrfirst2 v3 sequence for region #2 (first lines) 1e1 [0] 1 00 v3invfirst2 v3 sequence inversion for region #2 (first lines) 1e2 [3:0] 4 00 v3sptrsecond2 v3 sequence for region #2 (second lines) 1e3 [0] 1 00 v3invsecond2 v3 sequence inversion for region #2 (second lines) 1e4 [5:0] 6 00 v3_7start2[5:0] v3 and v7 sequence start for region #2 1e5 [5:0] 6 00 v3_7start2[11:6] 1e6 [3:0] 4 00 v4sptrfirst2 v4 sequence for region #2 (first lines) 1e7 [0] 1 00 v4invfirst2 v4 sequence inversion for region #2 (first lines) 1e8 [3:0] 4 00 v4sptrsecond2 v4 sequence for region #2 (second lines) 1e9 [0] 1 00 v4invsecond2 v4 sequence inversion for region #2 (second lines) 1ea [5:0] 6 00 v4_8start2[5:0] v4 and v8 sequence start for region #2 1eb [5:0] 6 00 v4_8start2[11:6] 1ec [5:0] 6 00 v1_4freeze2[5:0] v1 ? v4 freeze start position for region #2 1ed [5:0] 6 00 v1_4freeze2[11:6] 1ee [5:0] 6 00 v1_4resume2[5:0] v1 ? v4 resume start position for region #2 1ef [5:0] 6 00 v1_4resume2[11:6] 1f0 [5:0] 6 00 v5_8freeze2[5:0] v5 ? v8 freeze start position for region #2 1f1 [5:0] 6 00 v5_8freeze2[11:6] 1f2 [5:0] 6 00 v5_8resume2[5:0] v5 ? v8 resume start position for region #2 1f3 [5:0] 6 00 v5_8resume2[11:6] 1f4 [0] 1 00 sweep3 v sweep for region #3 1f5 [0] 1 00 multi3 v multiplier for region #3
rev. a e52e ad9891/ad9895 table xxviii. v1ev8 register map (continued) bit default address content width value register name register description 1f6 [5:0] 6 3f hdlen3[5:0] region #3 hd line length 1f7 [5:0] 6 3f hdlen3[11:6] 1f8 [1: 0] 20 0 hblksptr3 hblk s equence for region #3 1f9 [0] 10 0 vtpalt3 vtp sequence alternation for region #3 1fa [3:0] 4 00 v1sptrfirst3 v1 sequence for region #3 (first lines) 1fb [0] 1 00 v1invfirst3 v1 sequence inversion for region #3 (first lines) 1fc [3:0] 4 00 v1sptrsecond3 v1 sequence for region #3 (second lines) 1fd [0] 1 00 v1invsecond3 v1 sequence inversion for region #3 (second lines) 1fe [5:0] 6 00 v1_5start3[5:0] v1 and v5 sequence start for region #3 1ff [5:0] 6 00 v1_5start3[11:6] 200 [3:0] 4 00 v2sptrfirst3 v2 sequence for region #3 (first lines) 201 [0] 1 00 v2invfirst3 v2 sequence inversion for region #3 (first lines) 202 [3:0] 4 00 v2sptrsecond3 v2 sequence for region #3 (second lines) 203 [0] 1 00 v2invsecond3 v2 sequence inversion for region #3 (second lines) 204 [5:0] 6 00 v2_6start3[5:0] v2 and v6 sequence start for region #3 205 [5:0] 6 00 v2_6start3[11:6] 206 [3:0] 4 00 v3sptrfirst3 v3 sequence for region #3 (first lines) 207 [0] 1 00 v3invfirst3 v3 sequence inversion for region #3 (first lines) 208 [3:0] 4 00 v3sptrsecond3 v3 sequence for region #3 (second lines) 209 [0] 1 00 v3invsecond3 v3 sequence inversion for region #3 (second lines) 20a [5:0] 6 00 v3_7start3[5:0] v3 and v7 sequence start for region #3 20b [5:0] 6 00 v3_7start3[11:6] 20c [3:0] 4 00 v4sptrfirst3 v4 sequence for region #3 (first lines) 20d [0] 1 00 v4invfirst3 v4 sequence inversion for region #3 (first lines) 20e [3:0] 4 00 v4sptrsecond3 v4 sequence for region #3 (second lines) 20f [0] 1 00 v4invsecond3 v4 sequence inversion for region #3 (second lines) 210 [5:0] 6 00 v4_8start3[5:0] v4 and v8 sequence start for region #3 211 [5:0] 6 00 v4_8start3[11:6] 212 [5:0] 6 00 v1_4freeze3[5:0] v1 ? v4 freeze start position for region #3 213 [5:0] 6 00 v1_4freeze3[11:6] 214 [5:0] 6 00 v1_4resume3[5:0] v1 ? v4 resume start position for region #3 215 [5:0] 6 00 v1_4resume3[11:6] 216 [5:0] 6 00 v5_8freeze3[5:0] v5 ? v8 freeze start position for region #3 217 [5:0] 6 00 v5_8freeze3[11:6] 218 [5:0] 6 00 v5_8resume3[5:0] v5 ? v8 resume start position for region #3 219 [5:0] 6 00 v5_8resume3[11:6] 21a [0] 1 00 sweep4 v sweep for region #4 21b [0] 1 00 multi4 v multiplier for region #4 21c [5:0] 6 3f hdlen4[5:0] region #4 hd line length 21d [5:0] 6 3f hdlen4[11:6] 21e [1:0] 2 00 hblksptr4 hbl k sequence for region #4 21f [0] 10 0 vtpalt4 vtp sequence alternation for region #4 220 [3:0] 4 00 v1sptrfirst4 v1 sequence for region #4 (first lines) 221 [0] 1 00 v1invfirst4 v1 sequence inversion for region #4 (first lines) 222 [3:0] 4 00 v1sptrsecond4 v1 sequence for region #4 (second lines) 223 [0] 1 00 v1invsecond4 v1 sequence inversion for region #4 (second lines) 224 [5:0] 6 00 v1_5start4[5:0] v1 and v5 sequence start for region #4 225 [5:0] 6 00 v1_5start4[11:6] 226 [3:0] 4 00 v2sptrfirst4 v2 sequence for region #4 (first lines) 227 [0] 1 00 v2invfirst4 v2 sequence inversion for region #4 (first lines) 228 [3:0] 4 00 v2sptrsecond4 v2 sequence for region #4 (second lines) 229 [0] 1 00 v2invsecond4 v2 sequence inversion for region #4 (second lines) 22a [5:0] 6 00 v2_6start4[5:0] v2 and v6 sequence start for region #4 22b [5:0] 6 00 v2_6start4[11:6] 22c [3:0] 4 00 v4sptrfirst4 v4 sequence for region #4 (first lines)
rev. a ad9891/ad9895 e53e table xxviii. v1ev8 register map (continued) bit default address content width value register name register description 22d [0] 1 00 v4invfirst4 v4 sequence inversion for region #4 (first lines) 22e [3:0] 4 00 v4sptrsecond4 v4 sequence for region #4 (second lines) 22f [0] 1 00 v4invsecond4 v4 sequence inversion for region #4 (second lines) 230 [5:0] 6 00 v4_7start4[5:0] v4 and v7 sequence start for region #4 231 [5:0] 6 00 v4_7start4[11:6] 232 [3:0] 4 00 v4sptrfirst4 v4 sequence for region #4 (first lines) 233 [0] 1 00 v4invfirst4 v4 sequence inversion for region #4 (first lines) 234 [3:0] 4 00 v4sptrsecond4 v4 sequence for region #4 (second lines) 235 [0] 1 00 v4invsecond4 v4 sequence inversion for region #4 (second lines) 236 [5:0] 6 00 v4_8start4[5:0] v4 and v8 sequence start for region #4 237 [5:0] 6 00 v4_8start4[11:6] 238 [5:0] 6 00 v1_4freeze4[5:0] v1 ? v4 freeze start position for region #4 239 [5:0] 6 00 v1_4freeze4[11:6] 23a [5:0] 6 00 v1_4resume4[5:0] v1 ? v4 resume start position for region #4 23b [5:0] 6 00 v1_4resume4[11:6] 23c [5:0] 6 00 v5_8freeze4[5:0] v5 ? v8 freeze start position for region #4 23d [5:0] 6 00 v5_8freeze4[11:6] 23e [5:0] 6 00 v5_8resume4[5:0] v5 ? v8 resume start position for region #4 23f [5:0] 6 00 vtp5_8resume4[11:6] 240 [0] 1 01 vtp_sglinemode vtp second sequence output enable during sgline 241 [3:0] 4 02 v1sptr_sgline v1 second sequence 242 [0] 1 00 v1inv_sgline v1 second sequence inversion 243 [5:0] 6 10 v1start_sgline[5:0] v1 start position of second v pulse 244 [5: 0] 61 0 v1start_sgline[11:6] 245 [3:0] 4 03 v2sptr_sgline v2 second sequence 246 [0] 1 00 v2inv_sgline v2 second sequence inversion 247 [5:0] 6 2a v2start_sgline[5:0] v2 start position of second v pulse 248 [5: 0] 61 1 v2start_sgline[11:6] 249 [3:0] 4 04 v3sptr_sgline v3 second sequence 24a [0] 1 00 v3inv_sgline v3 second sequence inversion 24b [5:0] 6 32 v3start_sgline[5:0] v3 start position of second vtp pulse 24c [5:0] 6 0f v3start_sgline[11:6] 24d [3:0] 4 05 v4sptr_sgline v4 second sequence 24e [0] 1 00 v4inv_sgline v4 second sequence inversion 24f [5:0] 6 2e v4start_sgline[5:0] v4 start position of second vtp pulse 250 [5:0] 6 10 v4start_sgline[11:6]
rev. a e54e ad9891/ad9895 table xxix. vsg1evsg8 register map bit default address content width value register name register description 251 [0] 1 01 sgpol0 sequence #0: start polarity 252 [5:0] 6 22 sgtog1_0[5:0] sequence #0: toggle position 1 253 [5:0] 6 13 sgtog1_0[11:6] 254 [5:0] 6 1e sgtog2_0[5:0] sequence #0: toggle position 2 255 [5:0] 6 14 sgtog2_0[11:6] 256 [0] 1 01 sgpol1 sequence #1: start polarity 257 [5:0] 6 0c sgtog1_1[5:0] sequence #1: toggle position 1 258 [5:0] 6 11 sgtog1_1[11:6] 259 [5:0] 6 08 sgtog2_1[5:0] sequence #1: toggle position 2 25a [5:0] 6 12 sgtog2_1[11:6] 25b [0] 1 01 sgpol2 sequence #2: start polarity 25c [5:0] 6 3f sgtog1_2[5:0] sequence #2: toggle position 1 25d [5:0] 6 3f sgtog1_2[11:6] 25e [5:0] 6 3f sgtog2_2[5:0] sequence #2: toggle position 2 25f [5:0] 6 3f sgtog2_2[11:6] 260 [0] 1 01 sgpol3 sequence #3: start polarity 261 [5:0] 6 3f sgtog1_3[5:0] sequence #3: toggle position 1 262 [5:0] 6 3f sgtog1_3[11:6] 263 [5:0] 6 3f sgtog2_3[5:0] sequence #3: toggle position 2 264 [5:0] 6 3f sgtog2_3[11:6] 265 [5:0] 6 00 sgactlin e [5:0] vsg a ctive line 266 [4:0] 6 00 sgactline11:6] 267 [1:0] 2 00 sg sel1 vsg1 sequence selector 268 [1:0] 2 00 sg sel2 vsg2 sequence selector 269 [1:0] 2 00 sg sel3 vsg3 sequence selector 26a [1:0] 2 00 sg sel4 vsg4 sequence selector 26b [1:0] 2 01 sg sel5 vsg5 sequence selector 26c [1:0] 2 01 sg sel6 vsg6 sequence selector 26d [1:0] 2 01 sg sel7 vsg7 sequence selector 26e [1:0] 2 01 sg sel8 vsg8 sequence selector 26f [5:0] 6 00 sgmask[5:0] vsg masking (0 = output, 1 = mask) 270 [1:0] 2 00 sgmask[7:6] table xxx. subck, vsub, mshut register map bit default address content width value register name register description 271 [0] 1 01 subckpol subck start polarity 272 [5:0] 6 0b subck1tog1[5:0] first subck toggle position 1 273 [5:0] 6 01 subck1tog1[11:6] 274 [5:0] 6 05 subck1tog2[5:0] first subck toggle position 2 275 [5:0] 6 02 subck1tog2[11:6] 276 [5:0] 6 3f subck2tog1[5:0] second subck toggle position 1 277 [5:0] 6 3f subck2tog1[11:6] 278 [5:0] 6 3f subck2tog2[5:0] second subck toggle position 2 279 [5:0] 6 3f subck2tog2[11:6] 27a [5:0] 6 3f subcknum[5:0] num ber of subcks per field 27b [5:0] 6 00 subcknum[11:6] 27c [5:0] 6 00 subcksuppr ess number of sucks to suppress after vsg line 27d [5:0] 6 00 exposure[5:0] nu mber of fields to suppress subck/vsg (exposure time) 27e [5:0] 6 00 exposure[11:6] 27f [0] 1 00 vdhdoff disable vd and hd during exposure 280 [2:0] 3 00 trigger vsub (trigger[0]), mshut (trigger[1]), strobe (trigger[2]) trigger 28 1 [2:0] 3 02 readout subck suppression after exposure during readout 282 [0] 1 00 vsubmode vsub readout mode
rev. a ad9891/ad9895 e55e table xxx. subck, vsub, mshut register map (continued) bit default address content width value register name register description 283 [0] 1 00 vsubkeepon vsub off mode (0 = turn off after readout or next vd, 1 = keep active beyond readout) 284 [0] 1 01 vsubpol vsub active polarity 285 [5:0] 6 00 vsubon [5:0] vsub on position 286 [5:0] 6 00 vsubon[11:6] 287 [0] 1 00 mshuton mshut enable (vd aligned) 288 [0] 1 01 mshutpol mshut active polarity 289 [5:0] 6 00 ms hutonpos_ln[5:0] mshut on line position (in terms of hds from vd update) 28a [5: 0] 60 0 mshutonpos_ln[11:6] 28b [5:0] 6 00 mshutonpos_pix[5:0] mshut on pixel position (in terms of pixels from hd on position) 28c [5: 0] 60 0 mshutonpos_pix[11:6] 28d [5:0] 6 00 mshutoff_fd[5:0] mshut field off position (in terms of vds from field containing last subck) 28e [5:0] 6 00 mshutoff_fd[11:6] 28f [5:0] 6 00 mshutoff_ln[5:0] mshut line off position (in terms of hds from vd aligned off position) 290 [5:0] 6 00 mshutoff_ln[11:6] 291 [5:0] 6 00 mshutoff_px[5:0] mshut pixel off position (in terms of pixels from hd aligned off position) 292 [5:0] 6 00 mshutoff_px[11:6] 293 [0] 1 01 strobpol s trobe active polarity 294 [5:0] 6 00 strobon_fd[5:0] strobe field on position (in terms of vds from field containing last subck) 295 [5:0] 6 00 strobon_fd[11:6] 296 [5:0] 6 00 strobon_ln[5:0] strobe line on position (in terms of hds from vd aligned on position) 297 [5:0] 6 00 strobon_ln[11:6] 298 [5:0] 6 00 strobon_px[5:0] strobe pixel on position (in terms of pixels from hd aligned on position) 299 [5:0] 6 00 strobon_px[11:6] 29a [5:0] 6 00 stroboff_fd[5:0] strobe field off position (in terms of vds from field containing last subck) 29b [5:0] 6 00 stroboff_fd[11:6] 29c [5:0] 6 00 stroboff_ln[5:0] strobe line off position (in terms of hds from vd aligned off position) 29d [5:0] 6 00 stroboff_ln[11:6] 29e [5:0] 6 00 stroboff_px[5:0] strobe pixel off position (in terms of pixels from hd aligned off position) 29f [5:0] 6 00 stroboff_px[11:6]
rev. a e56e ad9891/ad9895 table xxxi. afe register breakdown bit default content width value register name register description oprmode [7:0] 8 ? h0 serial address: 10 ? h0{oprmode[5:0]}, 10 ? h1{oprmode[7:6]} [1:0] 2 ? h0 powerdown[1:0] norm al operation 2 ? h1 standby1 (see standby modes table) 2 ? h2 standby2 (see standby modes table) 2 ? h3 standby3 (see standby modes table) [2] disblack disable black loop clamping (high active) [3] test mode test mode ? should be set low [4] test mode test mode ? should be set high [5] test mode test mode ? should be set low [6] test mode test mode ? should be set low [7] test mode test mode ? should be set low ctlmode [5:0] 6 ? h0 serial address: 10 ? h6{cltmode[5:0]} [2:0] 3 ? h0 ctlmode[2:0] off 3 ? h1 mosaic separate 3 ? h2 vd selected/mosaic interlaced 3 ? h3 mosaic repeat 3 ? h4 3-color 3 ? h5 3-color ii 3 ? h6 4-color 3 ? h7 4-color ii [3] enablepxga enable pxga (high active) [4] 1 ? h0 outputlat latch output data on selected dout edge 1 ? h1 leave output latch transparent [5] 1 ? h0 tristateout adc outputs are driven 1 ? h1 adc outputs are three-stated
rev. a ad9891/ad9895 e57e outline dimensions 64-lead plastic ball grid array [cspbga] (bc-64) dimensions shown in millimeters a b c d e f g h j k bot tom view a1 top view detail a 1.70 max seating plane detail a ball diameter 0.25 min 10 9 8 7 6 5 4 3 2 1 9.00 bsc sq 7.20 bsc 0.90 ref sq 0.55 0.50 0.45 0.12 max coplanarity 0.80 bsc 0.85 min a1 corner index area compliant to jedec standards mo-205-ab revision history location page 8/02?data sheet changed from rev. 0 to rev. a. added ad9895 part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal
c02817e0e8/02(a) printed in u.s.a. e58e

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